scholarly journals A Comparative Study of Silicon Carbide Merged PiN Schottky Diodes with Electrical-Thermal Coupled Considerations

Materials ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2669
Author(s):  
Jiupeng Wu ◽  
Na Ren ◽  
Qing Guo ◽  
Kuang Sheng
Keyword(s):  
Silicon Carbide ◽  
Comparative Study ◽  
Thermal Resistance ◽  
Heat Dissipation ◽  
Schottky Diodes ◽  
Layout Design ◽  
Thermal Design ◽  
Junction Temperature ◽  
Bipolar Conduction ◽  
Surge Current

A comparative study of surge current reliability of 1200 V/5 A 4H-SiC (silicon carbide) MPS (Merged PiN Schottky) diodes with different technologies is presented. The influences of device designs in terms of electrical and thermal aspects on the forward conduction performance and surge current capability were studied. Device forward characteristics were simulated and measured. Standard single-pulse surge current tests and thermal impedance measurements were carried to show their surge capability and thermal design differences. An advanced thermal RC (thermal resistance-capacitance) model, with the consideration of current distribution non-uniformity effects, is proposed to accurately calculate the device junction temperature during surge events. It was found that a thinner substrate and a hexagonal layout design are beneficial to the improvement of the bipolar conduction performance in high current mode, as well as the surge current capability. The thinner substrate design also has advantages on thermal aspects, as it presents the lowest thermal resistance. The calculated failure temperature during the surge tests is consistent with the aluminum melting phenomenon, which is regarded as the failure mechanism. It was demonstrated that, for a SiC MPS diode, higher bipolar conduction performance is conducive to restraining the joule heat, and a lower thermal resistance design is able to accelerate the heat dissipation and limit the junction temperature during surge events. In this way, the MPS diode using a thinner substrate and advanced layout design technology is able to achieve 60% higher surge current density capability compared to the other technologies.

Design of a Cold Plate Tester for Accurate Measurement of Thermal Performance

2005 ◽  
Author(s):  
Nikhil Lakhkar ◽  
Madhusudan Iyengar ◽  
Michael Ellsworth ◽  
Dereje Agonafer
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
High Performance ◽  
Heat Dissipation ◽  
Thermal Design ◽  
Junction Temperature ◽  
Cold Plate ◽  
Expected Performance ◽  
Cold Plates ◽  
Effective Heat Transfer Coefficient

With the continuing industry trends towards smaller, faster and higher power devices, thermal management has become an extremely important element in the development of computer products. The primary goal of a good thermal design is to ensure that the chip can function at its rated frequency, while maintaining its junction temperature below the specified limit, to ensure reliable operation. The use of a heat sink or cold plate to manage the external thermal resistance has been well documented in the literature. However, the measurement of thermal performance of today state-of-the-art cold plates is challenging because of the low value of thermal resistance that they offer to heat dissipation. In this paper, the design of a tester apparatus for such high performance cold plates is presented. The expected performance of the tester is modeled numerically for a heat flux of 250 W/cm2, and for a range of footprint areas of 100-400 mm2. The analysis study is supported by a detailed uncertainty analysis that utilizes a Monte Carlo simulation approach. It was observed that the sum of random and repeatable errors could be controlled to within ±7.5% even for a very high performance cold plate with an effective heat transfer coefficient of 200,000 W/m2-K dissipating 250 W/cm2, with assumed errors in other relevant parameters.

SiC JFETs for Power Module Applications

2010 ◽  
Vol 645-648 ◽  
pp. 1167-1170 ◽  
Author(s):  
Jochen Hilsenbeck ◽  
Zhang Xi ◽  
Daniel Domes ◽  
Kathrin Rüschenschmidt ◽  
Michael Treu ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Thermal Resistance ◽  
Frequency Dependence ◽  
State Of The Art ◽  
Schottky Diodes ◽  
Power Module ◽  
Active Device ◽  
Switching Losses ◽  
Power Modules ◽  
Surge Current

Starting with the production of Infineon´s first silicon carbide (SiC) Schottky diodes in 2001, a lot of progress was achieved during recent years. Currently, a 3rd generation of MPS (merged pn Schottky) diodes is commercially available combining tremendous improvements with respect to surge current capability and reduced thermal resistance. In this work we present the implementation of SiC switches in power modules and a comparison of these units with the corresponding Si-based power modules. Also the frequency dependence of the total losses of the 1200V configurations using Si-IGBTs or SiC-JFETs as active device is shown, indicating that modules solution with a state of the art SiC JFET outperforms all other options for switching frequencies of 20 kHz and beyond. Additionally a total loss vs. frequency study will be presented. Furthermore, it is show that the switching losses of JFET based modules can be further reduced by reducing the internal distributed gate resistivity.

Analysis of Forward Surge Performance of SiC Schottky Diodes

2018 ◽  
Vol 924 ◽  
pp. 621-624 ◽  
Author(s):  
Rahul Radhakrishnan ◽  
Nathanael Cueva ◽  
Tony Witt ◽  
Richard L. Woodin
Keyword(s):  
Silicon Carbide ◽  
Failure Analysis ◽  
Ohmic Contact ◽  
Schottky Diodes ◽  
Forward Bias ◽  
Device Failure ◽  
Electrical Failure ◽  
The Impact ◽  
Surge Current

Silicon Carbide JBS diodes are capable, in forward bias, of carrying surge current of magnitude significantly higher than their rated current, for short periods. In this work, we examine the mechanisms of device failure due to excess surge current by analyzing variation of failure current with device current and voltage ratings, as well as duration of current surge. Physical failure analysis is carried out to correlate to electrical failure signature. We also quantify the impact, on surge current capability, of the resistance of the anode ohmic contact to the p-shielding region.

Approximate Analytical Model for a First Level Package With Non-Uniformly Powered Die

2006 ◽  
Author(s):  
Abhijit Kaisare ◽  
Dereje Agonafer ◽  
A. Haji-Sheikh ◽  
Greg Chrysler ◽  
Ravi Mahajan
Keyword(s):  
Thermal Resistance ◽  
Analytical Model ◽  
Functional Integration ◽  
Thermal Design ◽  
Junction Temperature ◽  
Direct Result ◽  
Design Guideline ◽  
Functional Blocks ◽  
Distribution Of Power ◽  
Functional Components

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.

Remarkable Increase in Surge Current Capability of SiC Schottky Diodes Using Press Pack Contacts

2013 ◽  
Vol 740-742 ◽  
pp. 873-876 ◽  
Author(s):  
Viorel Banu ◽  
Philippe Godignon ◽  
Xavier Jordá ◽  
Xavier Perpinya ◽  
José Millan
Keyword(s):  
Silicon Carbide ◽  
Power Density ◽  
Schottky Diodes ◽  
Experimental Results ◽  
Remarkable Increase ◽  
Surge Current

This work presents experimental results on surge current capability of SiC Schottky diodes performed on free floating press-pack encapsulation technologies. For the tests, we used a home-made workbench. The aim of our studies is to improve the current robustness and power density of Silicon Carbide (SiC) devices able to operate at temperatures over 300C°. Various technological approaches have to be considered, mainly on the interconnection technique and metallization layers in order to improve the power density and temperature operation of the diodes. Our investigation showed a strong improvement of electro-thermal performances, and especially the surge current capability that is almost doubled by using press-pack encapsulation.

Thermal resistance of high power LED influenced by ZnO thickness and surface roughness parameter

2016 ◽  
Vol 33 (1) ◽  
pp. 15-22 ◽  
Author(s):  
Shanmugan Subramani ◽  
Mutharasu Devarajan
Keyword(s):  
Thin Film ◽  
Surface Roughness ◽  
Thermal Resistance ◽  
Heat Sink ◽  
Heat Dissipation ◽  
Roughness Parameter ◽  
Junction Temperature ◽  
Zno Thin Film ◽  
Content Type ◽  
Cu Substrates

Purpose – The purpose of this research is to study the effect of thickness and surface properties of ZnO solid thin film for heat dissipation application in LED. Heat dissipation in electronic packaging can be improved by applying a thermally conductive interface material (TIM) and hence the junction temperature will be maintained. ZnO is one of the oxide materials and used as a filler to increase the thermal conductivity of thermal paste. The thickness of these paste-type material cannot be controlled which restricts the heat flow from the LED junction to ambient. The controlled thickness is only possible by using a solid thin-film interface material. Design/methodology/approach – Radio Frequency (RF)-sputtered ZnO thin film on Cu substrates were used as a heat sink for high-power LED and the thermal performance of various ZnO thin film thickness on changing total thermal resistance (R th-tot) and rise in junction temperature were tested. Thermal transient analysis was used to study the performance of the given LED. The influence of surface roughness profile was also tested on the LED performance. Findings – The junction temperature was high (6.35°C) for 200 nm thickness of ZnO thin film boundary condition when compared with bare Cu substrates. Consecutively, low R th-tot values were noticed with the same boundary condition. The 600 nm thickness of ZnO thin film exhibited high R th-tot and interface resistance than the other thicknesses. Bond Line Thickness of the interface material was influenced on the interface thermal resistance which was decreased with increased BLT. Surface roughness parameter showed an immense effect on thermal transport, and hence, low R th (47.6 K/W) value was noticed with low film roughness (7 nm) as compared with bare Cu substrate (50.8 K/W) where the surface roughness was 20.5 nm. Originality/value – Instead of using thermal paste, solid thin film ZnO is used as TIM and coated Cu substrates were used as a heat sink. The thickness can be controlled, and it is a new approach for reducing the BLT between the metal core printed circuit board and heat sink.

Thermal Analysis of High-Power LED Tube Lamp

2011 ◽  
Vol 308-310 ◽  
pp. 346-350 ◽  
Author(s):  
Xiang Jun Ma ◽  
Li Gang Wu ◽  
Shi Xun Dai ◽  
Bo You Zhou ◽  
Kun Bai ◽  
...  
Keyword(s):  
Finite Element Method ◽  
High Power ◽  
Heat Dissipation ◽  
Thermal Design ◽  
Junction Temperature ◽  
Key Technology ◽  
High Power Led ◽  
Detailed Simulation ◽  
Simulation Results ◽  
Thermal Grease

Heat dissipation of high-power LED lamps has become a key technology to LED package due to the improvement of the LED output power. A detailed simulation of temperature distribution of three chips high-power LED tube lamp was made by finite element method. Based on the consistency of the LED lamp experimental and simulation results, the analyses of the effect of thermal conductivities of PCB, thermal grease, heat sink, convection coefficients and the length of the lamp on the junction temperature were made, which provide an effective reference for the thermal design.

Research of 3.3kV, 60A H-Bridge High-Voltage SiC Diode Modules

2020 ◽  
Vol 1014 ◽  
pp. 163-170
Author(s):  
Feng Bin Hao ◽  
Xiao Xing Jin ◽  
Ao Liu ◽  
Shi Yan Li ◽  
Song Bai ◽  
...  
Keyword(s):  
Finite Element ◽  
High Voltage ◽  
Heat Dissipation ◽  
Voltage Drop ◽  
Geometric Model ◽  
Schottky Diodes ◽  
Safety Margin ◽  
Junction Temperature ◽  
Element Analysis ◽  
Gradient Distribution

The simulation, fabrication and measurement of the high-voltage H-bridge SiC diode module is reported. The SiC module is consisted with 8 self-designed 3.3 kV30 A SiC Schottky diodes (SBDs), in which each bridge arm is connected by double SBD chips to achieve 60A current. Q3D is used to establish simulation model and make network division of the module. Two parasitic parameters, parasitic inductor and circuit resistance, are extracted from the circuits, which are about 37.5 nH and 1.9 mΩ, respectively. By establishing the geometric model and finite element model, finite element analysis software ANSYS is used to calculate steady-state thermal conduction, and the temperature gradient distribution of the formed chips. The results show that the maximum junction temperature of the chip is about 100°C, and the distribution of the temperature field is reasonable. As the lateral conduction of heat increases the effective heat dissipation area, there is no obvious concentration of heat. Under the condition of the test at room temperature and static, the module voltage drop is about 2.1 V, the leakage current is less than 5 uA, and the breakdown voltage is more than 3700 V, respectively. The fabricated 3300 V devices exhibit large safety margin. The insulation voltage exceeds 7000V, thus ensure the safety of the system. The thermal resistance of the chip is about 0.21 K/W, which is basically consistent with the simulation results.

Heat Sink Cooling Fan and Rotation Speed Effect Analysis on Heat Dissipation of High Power GaN LED Package

2014 ◽  
Vol 1082 ◽  
pp. 315-318
Author(s):  
Rajendaran Vairavan ◽  
Vithyacharan Retnasamy ◽  
Zaliman Sauli ◽  
Hussin Kamarudin ◽  
Muammar Mohamad Isa ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
High Power ◽  
Heat Sink ◽  
Heat Dissipation ◽  
Rotation Speed ◽  
Junction Temperature ◽  
Von Mises Stress ◽  
Cooling Fan ◽  
High Power Led ◽  
Von Mises

In this work, thermal simulation analysis on high power LED is reported where the effect of the heat sink cooling fan and its rotation speed on the heat dissipation of the high power LED was evaluated. Ansys version 11 was utilized for the simulation. The thermal performance of the high power LED package was assessed in terms of operating junction temperature, von Mises stress and thermal resistance. The heat dissipation analysis was done under four types of convection condition:one natural convection conditionthree forced convection condition,. The forced convection condition was used to replicate the effect of a fan with various rotation speeds placed under the heat sink to increase the convective heat transfer coefficient. Results of the analysis showed that that the junction temperature, von Mises stress and thermal resistance of the GaN chip reduces with the increase of the fan rotation speed.

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