Investigation of Radiation Effects on FD-SOI Hall Sensors by TCAD Simulations

This work investigates the responses of the fully-depleted silicon-on-insulator (FD-SOI) Hall sensors to the three main types of irradiation ionization effects, including the total ionizing dose (TID), transient dose rate (TDR), and single event transient (SET) effects. Via 3D technology computer aided design (TCAD) simulations with insulator fixed charge, radiation, heavy ion, and galvanomagnetic transport models, the performances of the transient current, Hall voltage, sensitivity, efficiency, and offset voltage have been evaluated. For the TID effect, the Hall voltage and sensitivity of the sensor increase after irradiation, while the efficiency and offset voltage decrease. As for TDR and SET effects, when the energy deposited on the sensor during a nuclear explosion or heavy ion injection is small, the transient Hall voltage of the off-state sensor first decreases and then returns to the initial value. However, if the energy deposition is large, the transient Hall voltage first decreases, then increases to a peak value and decreases to a fixed value. The physical mechanisms that produce different trends in the transient Hall voltage have been analyzed in detail.

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Performance Optimization of FD-SOI Hall Sensors Via 3D TCAD Simulations

Sensors ◽

10.3390/s20102751 ◽

2020 ◽

Vol 20 (10) ◽

pp. 2751 ◽

Cited By ~ 1

Author(s):

Linjie Fan ◽

Jinshun Bi ◽

Kai Xi ◽

Sandip Majumdar ◽

Bo Li

Keyword(s):

Performance Optimization ◽

Computer Aided Design ◽

Transport Model ◽

Optimal Structure ◽

Physical Parameters ◽

Voltage Sensitivity ◽

Offset Voltage ◽

Trade Offs ◽

Hall Sensors ◽

Tcad Simulations

This work investigates the behavior of fully depleted silicon-on-insulator (FD-SOI) Hall sensors with an emphasis on their physical parameters, namely the aspect ratio, doping concentration, and thicknesses. Via 3D-technology computer aided design (TCAD) simulations with a galvanomagnetic transport model, the performances of the Hall voltage, sensitivity, efficiency, offset voltage, and temperature characteristics are evaluated. The optimal structure of the sensor in the simulation has a sensitivity of 86.5 mV/T and an efficiency of 218.9 V/WT at the bias voltage of 5 V. In addition, the effects of bias, such as the gate voltage and substrate voltage, on performance are also simulated and analyzed. Optimal structure and bias design rules are proposed, as are some adjustable trade-offs that can be chosen by designers to meet their own Hall sensor requirements.

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Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure

Electronics ◽

10.3390/electronics10131585 ◽

2021 ◽

Vol 10 (13) ◽

pp. 1585

Author(s):

Hanbin Wang ◽

Jinshun Bi ◽

Mengxin Liu ◽

Tingting Han

Keyword(s):

Gate Voltage ◽

Computer Aided Design ◽

Silicon On Insulator ◽

Fully Depleted ◽

Gate Structure ◽

Different Temperatures ◽

Dual Gate ◽

Sensitivity Changes ◽

Increasing Temperature ◽

Aided Design

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

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LoGHeD: An effective approach for negative differential resistance effect suppression in negative capacitance transistors

Semiconductor Science and Technology ◽

10.1088/1361-6641/ac4819 ◽

2022 ◽

Author(s):

Ziqiang Xie ◽

Weifeng Lyu ◽

Mengxue Guo ◽

Mengjie Zhao

Keyword(s):

Negative Differential Resistance ◽

Computer Aided Design ◽

Differential Resistance ◽

Silicon On Insulator ◽

Negative Capacitance ◽

Fully Depleted ◽

In Doping ◽

Drain Side ◽

Negative Differential Resistance Effect ◽

Aided Design

Abstract A negative capacitance transistor (NCFET) with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design (TCAD) simulation results have validated that the output conductance (GDS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (VTH), sub-threshold swing (SS), switching current ratio (ION/IOFF), and drain-induced barrier lowering (DIBL).

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Analysis of Orthogonal Coupling Structure Based on Double Three-Contact Vertical Hall Device

Micromachines ◽

10.3390/mi10090610 ◽

2019 ◽

Vol 10 (9) ◽

pp. 610

Author(s):

Rongshan Wei ◽

Yuxuan Du

Keyword(s):

Current Method ◽

Simulation Software ◽

Voltage Sensitivity ◽

Offset Voltage ◽

Coupling Structure ◽

Mapping Analysis ◽

Tcad Simulation ◽

Low Sensitivity ◽

Hall Sensors ◽

Low Offset

A vertical Hall device is an important component of 3D Hall sensors, used for detecting magnetic fields parallel to the sensor surface. The Hall devices described in existing research still have problems, such as large offset voltage and low sensitivity. Aiming to solve these problems, this study proposes a double three-contact vertical Hall device with low offset voltage, and a conformal mapping analysis method to improve the sensitivity of the device. Secondly, an orthogonal coupling structure composed of two sets of double three-contact vertical Hall devices is proposed, which further reduces the offset voltage of the device. Finally, the TCAD simulation software was used to analyze the performance of the devices, and an existing vertical Hall device was compared to ours. The results show that the orthogonal coupling structure in this study exhibits better performance, reaching an average voltage sensitivity of 17.5222 mV/VT and an average offset voltage of about 0.075 mV. In addition, the structure has the same magnitude of offset voltage in the four phases of the rotating current method. This characteristic enables the back-end circuit to more accurately filter out the offset voltage and acquire the Hall signal.

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LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

Fluctuation and Noise Letters ◽

10.1142/s021947750400194x ◽

2004 ◽

Vol 04 (02) ◽

pp. L345-L354 ◽

Cited By ~ 3

Author(s):

Y. HADDAB ◽

V. MOSSER ◽

M. LYSOWEC ◽

J. SUSKI ◽

L. DEMEUS ◽

...

Keyword(s):

Noise Level ◽

Low Voltage ◽

Silicon Layer ◽

Electrical Current ◽

Low Noise ◽

Silicon On Insulator ◽

Technological Parameters ◽

Wide Range ◽

Hall Sensors ◽

Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

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