scholarly journals The CMOS Highly Linear Current Amplifier with Current Controlled Gain for Sensor Measurement Applications

Sensors ◽  
2020 ◽  
Vol 20 (16) ◽  
pp. 4653
Author(s):  
Roman Prokop ◽  
Roman Sotner ◽  
Vilem Kledrowetz

This paper introduces a new current-controlled current-amplifier suitable for precise measurement applications. This amplifier was developed with strong emphasis on linearity leading to low total harmonic distortion (THD) of the output signal, and on linearity of the gain control. The presented circuit is characterized by low input and high output impedances. Current consumption is significantly smaller than with conventional quadratic current multipliers and is comparable in order to the maximum processed input current, which is ±200 µA. This circuit is supposed to be used in many sensor applications, as well as a precise current multiplier for general analog current signal processing. The presented amplifier (current multiplier) was designed by an uncommon topology based on linear sub-blocks using MOS transistors working in their linear region. The described circuit was designed and fabricated in a C035 I3T25 0.35-µm ON Semiconductor process because of the demand of the intended application for higher supply voltage. Nevertheless, the topology is suitable also for modern smaller CMOS technologies and lower supply voltages. The performance of the circuit was verified by laboratory measurement with parameters comparable to the Cadence simulation results and presented here.

2016 ◽  
Vol 64 (2) ◽  
pp. 301-306 ◽  
Author(s):  
B. Pankiewicz

Abstract In this paper the multiple output current amplifier basic cell is proposed. The triple output current mirror and current follower circuit are described in detail. The cell consists of a split nMOS differential pair and accompanying biasing current sources. It is suitable for low voltage operation and exhibits highly linear DC response. Through cell devices scaling, not only unity, but also any current gains are achievable. As examples, a current amplifier and bandpass biquad section designed in CMOS TSMC 90nm technology are presented. The current amplifier is powered from a 1.2V supply. MOS transistors scaling was chosen to obtain output gains equal to -2, 1 and 2. Simulated real gains are -1.941, 0.966 and 1.932 respectively. The 3dB passband obtained is above 20MHz, while current consumption is independent of input and output currents and is only 7.77μA. The bandpass biquad section utilises the previously presented amplifier, two capacitors and one resistor, and has a Q factor equal to 4 and pole frequency equal to 100 kHz.


2009 ◽  
Vol 18 (03) ◽  
pp. 519-534 ◽  
Author(s):  
COSMIN POPA

Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.


2020 ◽  
pp. 85-88 ◽  
Author(s):  
Nadezhda P. Kondratieva

The article describes the results of the study concerning the effect of the voltage level on current harmonic composition in greenhouses irradiators. It is found that its change affects the level of current harmonics of all types of the studied greenhouse irradiators. With decrease of nominal supply voltage by 10 %, the total harmonic distortion THDi decreases by 9 % for emitters equipped with high pressure sodium lamps (HPSL), by 10 % for emitters with electrode-less lamps and by 3 % for LED based emitters. With increase of nominal supply voltage by 10 %, THDi increases by 23 % for lighting devices equipped with HPSL, by 10 % for irradiators with electrode-less lamps and by 3 % for LED based emitters. Therefore, changes of supply voltage cause the least effect on the level of current harmonics of LED based emitters and then the emitters with electrode-less lamps. Change of the level of supply voltage causes the greatest effect on the level of current harmonics of HPSL based irradiators. Mathematical models of dependence of THDi on the level of supply voltage for greenhouse emitters equipped with LED, electrode-less lamps and HPSL lamps were formulated. These mathematical models may be used for calculations of total current when selecting transformers and supply cable lines for greenhouse lighting devices, for design of new or reconstruction of existing irradiation systems of greenhouse facilities, and for calculation of power losses in power supply networks of greenhouse facilities during feasibility studies for energy saving and energy efficiency increasing projects.


Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.


Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4092
Author(s):  
Grzegorz Blakiewicz ◽  
Jacek Jakusz ◽  
Waldemar Jendernalik

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.


2014 ◽  
Vol 15 (2) ◽  
pp. 177-194 ◽  
Author(s):  
Anup Kumar Panda ◽  
Ranjeeta Patel

Abstract In this paper, shoot-through current elimination DC–AC converter circuit has been presented with the application of active power filter (APF). The intuitive analysis of the shoot-through in the conventional DC–AC converter has been reported first. Interleaved buck (IB) converter is adopted to eliminate the shoot-through current, thereby increasing the reliability of the interleaved buck–based active power filter (IB-APF). The 3-phase 4-wire IB-APF eliminates the current harmonics produced by the load just as a conventional one does and are innately immune to “shoot-through” phenomenon, with the elimination of special protection features required in conventional inverter circuits. A comparison has been made about the compensation capabilities of the IB-APF with the PI and fuzzy logic controller (FLC) used by id–iq control strategy under different supply voltage conditions. The id–iq control strategy used for extracting the three-phase reference current for IB-APF, evaluating their performance here in MATLAB/Simulink environment and also implemented using real-time digital simulator hardware (OPAL-RT hardware). The RTDS result verifies that the total harmonic distortion percentage of the source current can be reduced below 5% according to IEEE-519 standard recommendations on harmonic limits.


2015 ◽  
Vol 645-646 ◽  
pp. 1308-1313
Author(s):  
Zhi Qiang Gao ◽  
Fu Xiang Huang ◽  
Jing Li ◽  
Liang Yin ◽  
Xiao Wei Liu

In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm2 of chip area.


Author(s):  
Peethala Rajiv Roy ◽  
P. Parthiban ◽  
B. Chitti Babu

Abstract This paper deals with implementation of a single-phase three level converter system under low voltage condition. The frequency of the switches is made constant and involves change in ${t_{on}}$ and ${t_{off}}$ duration. For this condition the pulse width modulation control scheme for a single phase three level rectifier is developed to improve the power quality. The hysteresis current control technique is adopted to bring forth three-level PWM on the dc side of the bridge rectifier and to achieve high power factor and low harmonic distortion. Based on the proposed control scheme, the line current is driven to follow the sinusoidal current command which is in phase with the supply voltage. By using three-level voltage pattern the blocking voltage of each power device is clamped to half of the dc link voltage. The simulation and experimental results of 20W converter under low input voltage condition are shown to verify the circuit performance. Open loop simulation and hardware tests are implemented by applying a low voltage of 15 V(rms) on the input side.


2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.


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