scholarly journals A Design of Adaptive Control and Communication Protocol for SWIPT System in 180 nm CMOS Process for Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 848
Author(s):  
Muhammad Riaz Ur Rehman ◽  
Imran Ali ◽  
Danial Khan ◽  
Muhammad Asif ◽  
Pervesh Kumar ◽  
...  
Keyword(s):  
Adaptive Control ◽  
Power Consumption ◽  
Communication Protocol ◽  
Power Splitting ◽  
Clock Frequency ◽  
Rf Power ◽  
Digital Clock ◽  
Ambient Environment ◽  
Sensor Applications ◽  
Rf Energy

This paper presents an adaptive control and communication protocol (ACCP) for the ultra-low power simultaneous wireless information and power transfer (SWIPT) system for sensor applications. The SWIPT system-related operations depend on harvested radio frequency (RF) energy from the ambient environment. The necessary power for SWIPT system operation is not always available and it depends on the available RF energy in the ambient environment, transmitted RF power from the SWIPT transmitter, and the distance from the transmitter and channel conditions. Thus, an efficient control and communication protocol is required which can control the SWIPT system for sensor applications which mainly consists of a transmitter and a receiver. Multiple data frame structures are used to optimize the exchange of bits for the communication and control of the SWIPT system. Both SWIPT transmitter and receiver are capable of using multiple modulation schemes which can be switched depending on the channel condition and the available RF energy in the ambient environment. This provides support for automatic switching between the time switching scheme and power splitting scheme for the distribution of received RF power in the SWIPT receiver. It also adjusts the digital clock frequency at the SWIPT receiver according to the harvested power level to optimize the power consumption. The SWIPT receiver controller with ACCP is implemented in 180 nm CMOS technology. The RF frequency of the SWIPT operation is 5.8 GHz. Digital clock frequency at the SWIPT receiver can be adjusted between 32 kHz and 2 MHz which provides data rates from 8 to 500 kbps, respectively. The power consumption and area utilization are 12.3 µW and 0.81 mm².

scholarly journals Study of Interaction Between Operational Clock-Frequency and Energy Consumption of Microcontrollers for Wireless Sensor Applications

2018 ◽  
Vol 192 ◽  
pp. 02042
Author(s):  
Subhawat Jayasvasti ◽  
Don Isarakorn
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Low Power ◽  
Processing Time ◽  
Wireless Sensor ◽  
Clock Frequency ◽  
Mathematical Equation ◽  
Sensor Application ◽  
Sensor Applications ◽  
Current Consumption

This work focuses on the diagnosis of energy consumption of commonly used microcontrollers with various driving clock-frequency. The interaction among the driving clock-frequency, processing time and current consumption are determined to be a guidance for the design of low-power wireless sensor applications. In implementation, the microcontrollers are supposed to process the data following the operational procedures of wireless sensor application, which is programmed to solve mathematical equation with various driving clock-frequencies, and then sleep to reduce the power consumption. With a single circle procession, the current consumption at each driving clock-frequency are captured and analyzed. As the results, the current consumption is proportional to the driving clock-frequency, however energy consumption is minimized at highest clock-frequency.

Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 55-62
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Brahamdeo Prasad Singh ◽  
Ajay Kumar
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Clock Frequency ◽  
Charge Sharing ◽  
Benchmark Circuit ◽  
Domino Circuit ◽  
Power Delay Product ◽  
Domino Circuits ◽  
Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

Effectiveness of DFS Tuning on Java Server Workload

2015 ◽  
Vol 25 (01) ◽  
pp. 1640005 ◽  
Author(s):  
Hitoshi Oi
Keyword(s):  
Power Consumption ◽  
Sampling Period ◽  
Threshold Level ◽  
Load Level ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Dynamic Frequency Scaling ◽  
Maximum Reduction ◽  
Dynamic Frequency

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.

scholarly journals RF Energy Harvesting with Multiple Sources in Wireless Mesh Network

2018 ◽  
Vol 10 (2) ◽  
pp. 606 ◽  
Author(s):  
K.N Puniran ◽  
Ahmad Robiah ◽  
Rudzidatul Akmam Dziyauddin
Keyword(s):  
Energy Harvesting ◽  
Base Station ◽  
Mesh Network ◽  
System Throughput ◽  
Power Splitting ◽  
Multiple Sources ◽  
Wireless Mesh ◽  
Optimal Value ◽  
Rf Energy ◽  
Single Relay

Energy harvesting (EH) module for wireless sensor network has become a promising feature to prolong the conventional battery inside the devices. This emerging technology is gaining interest from sensor manufacturers as well as academicians across the globe. The concept of employing EH module must be cost effective and practical. In such, the use of EH module type besides RF is more realistic due to the size of the scavenger module, the availability of the resources and conversion efficiency. Most of the oil and gas plants have some drawbacks in scavenging RF from surrounding (i.e. router, Wi-Fi, base station, cell phone) due to its placement in remote area and thus limited energy sources could be a threat in this application. Multiple sources, including co-channel interference (CCI) in any constraint nodes is a feasible way of scavenging several wastes from ambient RF energy via wireless mesh topology. In this paper, a 3-node decode-and-forward (DF) model is proposed where the relay node is subject to an energy constraint. Multiple primary sources and CCI are added in the system model known as Multiple-Source and Single-Relay (MSSR). A mathematical model is derived in Time Switching Relaying (TSR) and Power Splitting Relaying (PSR) schemes to obtain an average system throughput at a destination. Numerical simulation with respect to the average throughput and EH ratio was performed and compared with the Single-Source and Single-Relay (SSSR) and ideal receiver. By applying multiple sources and CCI as an energy enhancement at the constraint node, the optimal value of EH ratio for TSR can be reduced significantly by 10% as compared to the ideal receiver whereas the optimal value of EH ratio for PSR is outweigh TSR in terms of overall system throughput.

The Research and Design of the Adaptive Pulse Demagnetizer

2012 ◽  
Vol 182-183 ◽  
pp. 427-430
Author(s):  
Li Feng Wei ◽  
Liang Cheng ◽  
Xing Man Yang
Keyword(s):  
Adaptive Control ◽  
Power Consumption ◽  
Low Power ◽  
Control Method ◽  
Experimental Results ◽  
Low Power Consumption ◽  
Reliable Operation ◽  
Charge Current ◽  
Long Life ◽  
Research And Design

A adaptive control method of the pulse demagnetizer was presented, Can adjust the strength of the charge current automatically according to the changes of the magnetic content to ensure the constant of the magnetic field.The experimental results have shown that it has the advantages of low power consumption, strong anti-interference capability, stable and reliable operation, long life and good demagnetizing effect, when compared to the conventional demagnetizers.

scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

scholarly journals Compact Rectifier Circuit Design for Harvesting GSM/900 Ambient Energy

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1614
Author(s):  
Surajo Muhammad ◽  
Jun Jiat Tiang ◽  
Sew Kin Wong ◽  
Amjad Iqbal ◽  
Mohammad Alibakhshikenari ◽  
...  
Keyword(s):  
Circuit Design ◽  
Communication Systems ◽  
Path Loss ◽  
Input Power ◽  
Wireless Communication Systems ◽  
Rf Power ◽  
Total Size ◽  
High Input Power ◽  
Wide Range ◽  
Rf Energy

In this paper, a compact rectifier, capable of harvesting ambient radio frequency (RF) power is proposed. The total size of the rectifier is 45.4 mm × 7.8 mm × 1.6 mm, designed on FR-4 substrate using a single-stage voltage multiplier at 900 MHz. GSM/900 is among the favorable RF Energy Harvesting (RFEH) energy sources that span over a wide range with minimal path loss and high input power. The proposed RFEH rectifier achieves measured and simulated RF-to-dc (RF to direct current) power conversion efficiency (PCE) of 43.6% and 44.3% for 0 dBm input power, respectively. Additionally, the rectifier attained 3.1 V DC output voltage across 2 kΩ load terminal for 14 dBm and is capable of sensing low input power at −20 dBm. The work presents a compact rectifier to harvest RF energy at 900 MHz, making it a good candidate for low powered wireless communication systems as compares to the other state of the art rectifier.

Rectenna panel design optimization for maximum RF power utilization

2019 ◽  
Vol 11 (10) ◽  
pp. 1024-1034
Author(s):  
Vinita Daiya ◽  
Jemimah Ebenezer ◽  
R. Jehadeesan
Keyword(s):  
Design Parameters ◽  
Far Field ◽  
Rf Power ◽  
Transfer Energy ◽  
Grid Pattern ◽  
Antenna Aperture ◽  
Power Requirement ◽  
Efficient System ◽  
Rf Energy ◽  
Panel Design

AbstractNow-a-days, far-field wireless power transfer/energy harvesting is underutilized due to the unavailability of proper methodology to design efficient system for maximum radio frequency (RF) power utilization. For efficient utilization of far-field RF energy an array/grid of rectenna, i.e. rectenna panel is required to generate the power from wireless signal. To minimize the engineering design phase period (design trials), this paper mathematically derives and summarizes the approach required for optimum rectenna panel design based on power available in the environment, RF transmit source capability, receiver power requirement and the design cost. For maximum power interception through a rectenna panel, its design parameters such as -panel size, number of rectenna, rectenna arrangement pattern, and rectenna spacing has been optimized in our work. Based on the optimization required, we have proposed the compact grid pattern with heterogeneous rectenna spacing. It has been proved theoretically in this paper that if a hexagonal shape panel is designed by placement of rectenna at vertices of equilateral triangle (with side length governed by antenna aperture) then, it is capable of intercepting maximum RF energy available at its location with the least number of rectenna.

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