scholarly journals Detection of an IL-6 Biomarker Using a GFET Platform Developed with a Facile Organic Solvent-Free Aptamer Immobilization Approach

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1335
Author(s):  
Niazul I. Khan ◽  
Edward Song

Aptamer-immobilized graphene field-effect transistors (GFETs) have become a well-known detection platform in the field of biosensing with various biomarkers such as proteins, bacteria, virus, as well as chemicals. A conventional aptamer immobilization technique on graphene involves a two-step crosslinking process. In the first step, a pyrene derivative is anchored onto the surface of graphene and, in the second step, an amine-terminated aptamer is crosslinked to the pyrene backbone with EDC/NHS (1-ethyl-3-(3-dimethylaminopropyl) carbodiimide hydrochloride/N-hydroxysuccinimide) chemistry. However, this process often requires the use of organic solvents such as dimethyl formamide (DMF) or dimethyl sulfoxide (DMSO) which are typically polar aprotic solvents and hence dissolves both polar and nonpolar compounds. The use of such solvents can be especially problematic in the fabrication of lab-on-a-chip or point-of-care diagnostic platforms as they can attack vulnerable materials such as polymers, passivation layers and microfluidic tubing leading to device damage and fluid leakage. To remedy such challenges, in this work, we demonstrate the use of pyrene-tagged DNA aptamers (PTDA) for performing a one-step aptamer immobilization technique to implement a GFET-based biosensor for the detection of Interleukin-6 (IL-6) protein biomarker. In this approach, the aptamer terminal is pre-tagged with a pyrene group which becomes soluble in aqueous solution. This obviates the need for using organic solvents, thereby enhancing the device integrity. In addition, an external electric field is applied during the functionalization step to increase the efficiency of aptamer immobilization and hence improved coverage and density. The results from this work could potentially open up new avenues for the use of GFET-based BioMEMS platforms by broadening the choice of materials used for device fabrication and integration.

Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions


2021 ◽  
Vol 25 ◽  
pp. 100730
Author(s):  
Hui Ding ◽  
Weijun Yang ◽  
Wenhao Yu ◽  
Tianxi Liu ◽  
Haigang Wang ◽  
...  

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
M. Rajabali ◽  
H. Asgharyan ◽  
V. Fadaei Naeini ◽  
A. Boudaghi ◽  
B. Zabihi ◽  
...  

AbstractLow concentration phosphorene-based sensors have been fabricated using a facile and ultra-fast process which is based on an exfoliation-free sequential hydrogen plasma treatment to convert the amorphous phosphorus thin film into mono- or few-layered phosphorene sheets. These sheets have been realized directly on silicon substrates followed by the fabrication of field-effect transistors showing the low leakage current and reasonable mobility for the nano-sensors. Being capable of covering the whole surface of the silicon substrate, red phosphorus (RP) coated substrate has been employed to achieve large area phosphorene sheets. Unlike the available techniques including mechanical exfoliation, there is no need for any exfoliation and/or transfer step which is significant progress in shortening the device fabrication procedure. These phosphorene sheets have been examined using transmission electron microscopy (TEM), Scanning electron microscopy (SEM), Raman spectroscopy and atomic-force microscopy (AFM). Electrical output in different states of the crystallization as well as its correlation with the test parameters have been also extensively used to examine the evolution of the phosphorene sheets. By utilizing the fabricated devices, the sensitivity of the phosphorene based-field effect transistors to the soluble L-Cysteine in low concentrations has been studied by measuring the FET response to the different concentrations. At a gate voltage of − 2.5 V, the range of 0.07 to 0.60 mg/ml of the L-Cysteine has been distinguishably detected presenting a gate-controlled sensor for a low-concentration solution. A reactive molecular dynamics simulation has been also performed to track the details of this plasma-based crystallization. The obtained results showed that the imparted energy from hydrogen plasma resulted in a phase transition from a system containing red phosphorus atoms to the crystal one. Interestingly and according to the simulation results, there is a directional preference of crystal growth as the crystalline domains are being formed and RP atoms are more likely to re-locate in armchair than in zigzag direction.


2020 ◽  
Vol 1008 ◽  
pp. 33-38
Author(s):  
Marwa Nabil ◽  
Hussien A. Motaweh

Silica is one of the most important materials used in many industries. The basic factor on which the selection process depends is the structural form, which is dependent on the various physical and chemical properties. One of the common methods in preparing pure silica is that it needs more than one stage to ensure the preparation process completion. The goal of this research is studying the nucleation technique (Bottom-top) for micro-wires and micro-ribbons silica synthesis. The silica nanoand microstructures are prepared using a duality (one step); a combination of alkali chemical etching process {potassium hydroxide (3 wt %) and n-propanol (30 Vol %)} and the ultra-sonication technique. In addition, the used materials in the preparation process are environmentally friendly materials that produce no harmful residues. The powder product is characterized using XRD, FTIR, Raman spectrum and SEM for determining the shape of architectures. The most significant factor of the nucleation mechanism is the sonication time of silica powder production during the dual technique. The product stages are as follows; silica nanoparticles (21-38 nm), nanoclusters silica (46 – 67 nm), micro-wires silica (1.17 – 6.29 μm), and micro-ribbons silica (19.4 – 54.1 μm). It's allowing for use in environmental applications (multiple wastewater purification, multiple uses in air filters, as well as many industrial applications).


Author(s):  
Akiyoshi Inoue ◽  
Sakura Tanaka ◽  
Takashi Egawa ◽  
Makoto Miyoshi

Abstract In this study, we fabricated and characterized heterojunction field-effect transistors (HFETs) based on an Al0.36Ga0.64N-channel heterostructure with a dual AlN/AlGaInN barrier layer. The device fabrication was accomplished by adopting a regrown n++-GaN layer for ohmic contacts. The fabricated HFETs with a gate length of 2 μm and a gate-to-drain distance of 6 μm exhibited an on-state drain current density as high as approximately 270 mA/mm and an off-state breakdown voltage of approximately 1 kV, which corresponds to an off-state critical electric field of 166 V/μm. This breakdown field, as a comparison in devices without field-plate electrodes, reaches approximately four-fold higher than that for conventional GaN-channel HFETs and was considered quite reasonable as an Al0.36Ga0.64N-channel transistor. It was also confirmed that the devices adopting the dual AlN/AlGaInN barrier layer showed approximately one order of magnitude smaller gate leakage currents than those for devices without the top AlN barrier layer.


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