scholarly journals A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits

Sensors ◽  
2021 ◽  
Vol 21 (23) ◽  
pp. 7856
Author(s):  
Jianyu Zhang ◽  
Pak Kwong Chan
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Output Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Process Technology ◽  
Operation Condition ◽  
Worst Case ◽  
Operation Temperature

A new power supply rejection (PSR) based enhancer with small and stable dropout voltage is presented in this work. It is implemented using TSMC-40 nm process technology and powered by 1.2 V supply voltage. A number of circuit techniques are proposed in this work. These include the temperature compensation for Level-Shifted Flipped Voltage Follower (LSFVF) and the Complementary-To-Absolute Temperature (CTAT) current reference. The typical output voltage and dropout voltage of the enhancer is 1.1127 V and 87.3 mV, respectively. The Monte-Carlo simulation of this output voltage yields a mean T.C. of 29.4 ppm/°C from −20 °C and 80 °C. Besides, the dropout voltage has been verified with good immunity against Process, Temperature and Process (PVT) variation through the worst-case simulation. Consuming only 4.75 μA, the circuit can drive load up to 500 μA to yield additional PSR improvement of 36 dB and 20 dB of PSR at 1 Hz and 1 MHz, respectively for the sensor circuit of interest. This is demonstrated through the application of an enhancer on the instrumentation Differential Difference Amplifier (DDA) for sensing floating bridge sensor signal. The comparative Monte-Carlo simulation results on a respective DDA circuit have revealed that the process sensitivity of output voltage of this work has achieved 14 times reduction in transient metrics with respect to that of the conventional counterpart over the operation temperature range in typical operation condition. Due to simplicity without voltage reference and operational amplifier(s), low power and small consumption of supply voltage headroom, the proposed work is very useful for supply noise sensitive analog or sensor circuit applications.

A New No Op Amp Full CMOS Voltage Reference Circuit

2014 ◽  
Vol 519-520 ◽  
pp. 1067-1070
Author(s):  
Jian Ying Shi ◽  
Hui Ya Li ◽  
Yan Bin Xu
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Output Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Op Amp ◽  
Reference Circuit ◽  
Simulation Results ◽  
Cmos Voltage Reference

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.

scholarly journals CMOS Voltage Reference using a Self-Cascode Composite Transistor and a Schottky Diode

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary
Keyword(s):  
Schottky Diode ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Silicon Area ◽  
Circuit Topology ◽  
Voltage Range ◽  
Self Cascode ◽  
Cmos Voltage Reference ◽  
The Impact

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.

A High-Order CMOS Bandgap Voltage Reference

2014 ◽  
Vol 989-994 ◽  
pp. 1165-1168
Author(s):  
Qian Neng Zhou ◽  
Yun Song Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
High Order ◽  
Cmos Process ◽  
Voltage Reference ◽  
Power Supply Voltage ◽  
Power Supply Rejection Ratio ◽  
Voltage Deviation ◽  
Bandgap Voltage Reference

A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.

scholarly journals A low quiescent current low dropout voltage regulator with self-compensation

2019 ◽  
Vol 8 (1) ◽  
pp. 65-73
Author(s):  
Chu-Liang Lee ◽  
Roslina Mohd Sidek ◽  
Nasri Sulaiman ◽  
Fakhrul Zaman Rokhani
Keyword(s):  
Supply Voltage ◽  
Drop Out ◽  
Voltage Regulator ◽  
Cmos Process ◽  
Process Technology ◽  
Worst Case ◽  
Unity Gain ◽  
Quiescent Current ◽  
Additional Current ◽  
Loop Stability

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.

scholarly journals A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift

2018 ◽  
Vol 27 (08) ◽  
pp. 1850128 ◽  
Author(s):  
R. Nagulapalli ◽  
K. Hayatleh ◽  
Steve Barker ◽  
Sumathi Raparthy ◽  
Nabil Yassine ◽  
...  
Keyword(s):  
Power Supply ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Temperature Drift ◽  
Ultra Low Power

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65[Formula: see text]nm CMOS has been developed and occupies 0.0039[Formula: see text]mm2, and at room temperature, it generates a 204[Formula: see text]mV reference voltage with 1.3[Formula: see text]mV drift over a wide temperature range (from [Formula: see text]40[Formula: see text]C to 125[Formula: see text]C). This has been designed to operate with a power supply voltage down to 0.6[Formula: see text]V and consumes 1.8[Formula: see text]uA current from the supply. The simulated temperature coefficient is 40[Formula: see text]ppm/[Formula: see text]C.

scholarly journals Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters

2021 ◽  
Author(s):  
Mateus B. Castro ◽  
Raphael R. N. Souza ◽  
Agord M. P. Junior ◽  
Eduardo R. Lima ◽  
Leandro T. Manera
Keyword(s):  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Phase Locked Loop ◽  
Analog To Digital Converters ◽  
Cmos Process ◽  
Reference Frequency ◽  
Process Technology ◽  
Worst Case ◽  
Sigma Delta ◽  
Analog To Digital

AbstractThis paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The synthesizer was implemented in TSMC 65 nm CMOS process technology and the presented results were obtained from extracted layout view with parasitics. The synthesizer generates clock frequencies ranging from 40 to 230 MHz considering a reference frequency of 10 MHz and a supply voltage of 1.2 V. Worst case current consumption is 634 $$\mu $$ μ W, settling time is 6 $$\mu $$ μ s, maximum jitter is 1.3 ns in a 0.037 mm$$^2$$ 2 area. Performance was validated in a test $$\Sigma \Delta $$ Σ Δ Modulator with bandwidths of 200 kHz, 500 kHz and 2 MHz, and oversampling frequencies of 40, 60 and 80 MHz respectively, with negligible signal-to-noise ratio degradation compared to an ideal clock.

scholarly journals A 167.18 ppm/°C temperature coefficient, area efficient voltage reference using only MOS transistors

2020 ◽  
Vol 17 (1) ◽  
pp. 31-40
Author(s):  
Guru Prasad ◽  
Kumara Shama
Keyword(s):  
Temperature Coefficient ◽  
Room Temperature ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Inversion Region ◽  
Strong Inversion ◽  
Reference Circuit ◽  
Simulation Results

In this paper, design of a voltage reference circuit using only MOS transistors and without employing an operational amplifier is presented. A proportional to absolute temperature [PTAT] voltage and a PTAT current are designed then difference of the PTAT voltage and product of the PTAT current and resistor gives the temperature independent voltage. The advantages of both sub-threshold and strong inversion region operation of MOS transistors are exploited in the design. The voltage reference is implemented using standard CMOS 180 nm technology. The voltage reference provides a voltage of 224.3 mV consuming a quiescent current of 30 ?A at room temperature. Post layout simulation results show that the proposed voltage reference has a temperature coefficient of 167.18 ppm/?C and varies only 3mV when there is a ?10% variation in supply voltage. The circuit occupies an area of only 93.6?32.6?m on the chip, making it suitable for area constraint applications.

A High Order Curvature-Compensated Bandgap Voltage Reference with a Novel Error Amplifier

2017 ◽  
Vol 26 (09) ◽  
pp. 1750127 ◽  
Author(s):  
Gongyuan Zhao ◽  
Mao Ye ◽  
Yiqiang Zhao ◽  
Kai Hu ◽  
Ruishan Xin
Keyword(s):  
Monte Carlo Simulation ◽  
Power Supply ◽  
Supply Voltage ◽  
High Order ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Dependent ◽  
Error Amplifier ◽  
Bandgap Voltage Reference ◽  
Simulation Results

This paper presents a bandgap voltage reference (BGR), utilizing high order curvature-compensated technique with the temperature dependent resistor. Based on an improved error amplifier, [Formula: see text]80[Formula: see text]dB power supply rejection (PSR) @1[Formula: see text]kHz is achieved without additional complicated circuits. The circuit is fabricated in a standard [Formula: see text]m CMOS process, consuming 50[Formula: see text][Formula: see text]A at 25[Formula: see text]C with a supply voltage of 3.3[Formula: see text]V. Simulation results show that the proposed BGR can achieve a temperature coefficient as low as 1.18[Formula: see text]ppm/[Formula: see text]C over the temperature range from [Formula: see text]C to 120[Formula: see text]C. Monte Carlo simulation and Experimental Results validate the design.

Probabilistic Lifing Methods for Digital Assets

2020 ◽  
Author(s):  
Henry Cathcart ◽  
Christopher Meyer ◽  
Mark Joyce ◽  
Richard Green
Keyword(s):  
Monte Carlo ◽  
Fatigue Damage ◽  
Gas Turbines ◽  
Life Extension ◽  
Operation Condition ◽  
Worst Case ◽  
Hot Gas ◽  
Creep Fatigue ◽  
Operational Data ◽  
Digital Assets

Abstract Modern industrial gas turbines (IGTs) must be capable of operational flexibility to fulfil the requirements of an evolving power industry. Base load applications require turbines to operate for long periods at full load conditions whilst load-following applications require turbines to undergo repeated start-stop cycles. Traditional design and lifing approaches, which are based around an assumed worst case operational scenario and critical damage mechanism, cannot fully represent the durability of components when exposed to flexible operation. Condition based assessments, conversely, consider multiple operating scenarios and damage mechanisms to more accurately predict the durability of components. Condition based assessments are particularly powerful when applied to digital assets, where component lives can be calculated for each individual turbine based on detailed operational data. Despite the additional data available to conduct assessments of a digital asset, the information about the asset’s manufacture, maintenance or environment is unlikely to be complete or perfect. This leads to uncertainty in the current and future condition of the asset, which must be accounted for when deciding upon maintenance, retirement or life extension. The uncertainty can be accounted for using bounding assumptions or safety factors, but these approaches often lead to overly conservative results and do not provide any insight into the underlying causes of the uncertainty. Probabilistic methodologies provide a means to accurately evaluate and interrogate this uncertainty, by explicitly considering the potential variation in calculation inputs and assumptions. The degradation of hot gas path components by creep-fatigue mechanisms often limits turbine life. Probabilistic creep-fatigue assessment methods have been developed and are used to predict and understand the uncertainty in creep-fatigue damage. However, deploying these methods across a large fleet of digital assets, each with multiple components presents several challenges: the assessments rely on Monte Carlo sampling or other discretised calculations and hence are too computationally intensive to be used in real time on a large fleet; assets have often not been digitized for their entire operating lives, hence periods of missing data must be accounted for; finally, predicting the uncertainty of future operation requires information about the likely distribution of future operating regimes. This paper presents a methodology to effectively calculate the uncertainty on hot gas path component creep-fatigue assessments across a large fleet of IGTs. The methodology divides operational periods into two categories. In the first category a full suite of operational data is available. Damage is modelled using an emulator of a full Monte Carlo assessment. The emulator accounts for the fact that different operational profiles may result in different degradation uncertainty, and that the mode of operation of an asset may change throughout its life. In the second category no information is available. This category covers both future operation and historical operation prior to the instrumentation of the asset. These periods are modelled by considering fleet-wide statistics of degradation and the pathdependency of creep-fatigue damage progression. The predictions for both categories of operation are integrated into a system that can predict distributions of the damage accumulated within a turbine component and the future progression of this damage.

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