Subthreshold Current Modeling of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET For Low Power Applications

2021 ◽  
Author(s):  
Prashant Kumar ◽  
Munish Vashisht ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Future Generation ◽  
Threshold Current ◽  
Cmos Inverter ◽  
Drive Current ◽  
Subthreshold Current ◽  
Pmos Transistor ◽  
Good Agreement ◽  
The Ideal

Abstract Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctioless MOSFET. The analytical results were compared with TMSG MOSFET and good agreement was obtained. The sub-threshold current of the device is very low and consider for the implementation of CMOS inverter. A PMOS transistor is designed and the drive current of the PMOS transistor is tuned with the NMOS device to obtain the ideal matching in the drive current. A CMOS inverter has been designed. The transient and DC behavior of the device have been examined. The power dissipation of the CMOS inverter has been computed and compared with CMOS DMG-SOI JLT inverter. The power dissipation is 5 times less in proposed device as compared to CMOS DMG-SOI JLT inverter. This exhibits an excellent improvement in power dissipation which is useful for making low power future generation devices.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

scholarly journals Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

2021 ◽  
Vol 10 (6) ◽  
pp. 1-10
Author(s):  
S.C. Wagaj ◽  
◽  
S.C. Patil ◽  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
Junctionless Transistor ◽  
Dual Gate ◽  
Static Power

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

AN EFFICIENT LOW-SWING MULTITHRESHOLD-VOLTAGE LOW-POWER DESIGN TECHNIQUE

2004 ◽  
Vol 13 (01) ◽  
pp. 193-203
Author(s):  
A. RJOUB ◽  
M. ALROUSAN ◽  
O. ALJARRAH ◽  
O. KOUFOPAVLOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Output Voltage ◽  
Supply Voltage ◽  
Low Power Design ◽  
Design Technique ◽  
Cmos Inverter ◽  
Spice Simulation ◽  
Comparison Results ◽  
Simulation Results

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 * 16-bit multiplier is implemented by using the proposed technique in 0.25μm silicon technology.

scholarly journals Implementation and modeling of low power sleepy stack SRAM cell

2019 ◽  
Vol 2 (1) ◽  
pp. 53-56
Author(s):  
Manvinder Sharma ◽  
Dishant Khosla ◽  
Sohni Singh ◽  
Pankaj Palta
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Memory Cell ◽  
Threshold Current ◽  
Heat Emission ◽  
Leakage Power ◽  
Sram Cell ◽  
Future Technologies

for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

Low Power dissipation of Ring Counter using Dual sleep Transistor approach

2014 ◽  
Vol 4 (3) ◽  
pp. 9-13
Author(s):  
M. Balaji ◽  
◽  
B. Keerthana ◽  
K. Varun ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Ring Counter ◽  
Low Power Dissipation

An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET

2019 ◽  
Vol 9 (2) ◽  
pp. 291-297
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Ahmed Bouziane ◽  
Benjamin Iñiguez
Keyword(s):  
Current Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Subthreshold Current ◽  
The Poisson Equation ◽  
Strong Inversion ◽  
Cylindrical Form ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Good Agreement

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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