scholarly journals Design of Low Power Adders in Digital Circuits Suitable for Power Reduction in Multipliers

2020 ◽  
Vol 9 (3) ◽  
pp. 1657-1662
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Circuits ◽  
Evolutionary Process ◽  
Full Adder ◽  
Power Reduction ◽  
Wireless Devices ◽  
Xor Gate ◽  
Core Areas ◽  
Static Energy

Wireless devices are being evolved at an exponential rate. This evolution is focussing on the development of digital circuits which are incorporated into the processors. The evolutionary process involves individually or a combination of three main objectives namely i) Reduction in size ii) Reduction in power iii) Increase in speed. There is always a trade-off among the above said objectives. In specific multiplying operation inside a processor is one of the core areas where much power is being consumed. On the other hand adders are an integral part in the multiplier circuit. So this work concentrates on designing and analyzing power consumption of five adders namely conventional full adder, 3-transistor XOR based full adder, Gate Diffusion Input (GDI) based full adder, Static Energy Recovery Full (SERF) Adder and full adder using modified XOR gate and finding a resultant low power adder which when implemented for the addition process in multiplier will lead to a reduction in power consumption of multiplier. This in turn reduce the overall power consumption of the processor. The adders are designed using LTSPICE XVII in 180nm technology. The resultant Full Adder using modified XOR gate achieves 61.79% less power compared to conventional full adder and is suitable for multipliers.

scholarly journals A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

2019 ◽  
Vol 8 (3) ◽  
pp. 162
Author(s):  
Pritty Pritty ◽  
Manoj Kumar ◽  
Mariyam Zunairah
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Full Adder ◽  
Digital Circuit ◽  
Xor Gate ◽  
Digital Circuit Design ◽  
Result Show ◽  
Body Bias

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

scholarly journals AREA AND POWER OPTIMIZED D-FLIP FLOP AND SUBTRACTOR

2021 ◽  
Vol 9 (1) ◽  
pp. 159-163
Author(s):  
T. Subhashini, M. Kamaraju, K. Babulu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Modern Technology ◽  
Power Reduction ◽  
Flip Flop ◽  
Xor Gate ◽  
Long Run

Low power is essential in today’s technology. It is most significant with high speed, small size and stability. So, power reduction is most important in modern technology using VLSI design techniques. Today most of the market necessities require low power, long run time and market which also deserve small size and high speed. In this paper several logic circuits DFF with 5 transistors and sub tractor circuit using powerless XOR gate and Groundless XNOR gates are implemented. In the proposed DFF, the area can be decreased by 62% & substarctor circuit, area decreased by 80% and power consumption of DFF and subtractor circuit are 15.4µW and 13.76µW respectively, but these are very less as compared to existing techniques.  

scholarly journals HIGH SPEED ADDER USING GDI TECHNIQUE

2020 ◽  
Vol 5 (2) ◽  
pp. 130-136
Author(s):  
Merrin Mary Solomon ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Full Adder ◽  
Low Complexity ◽  
Propagation Delay ◽  
Logic Design ◽  
Reduce Power Consumption

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices

2016 ◽  
Vol 95 (2) ◽  
pp. 353-364 ◽  
Author(s):  
Gaurav Verma ◽  
Manish Kumar ◽  
Vijay Khare ◽  
Bishwajeet Pandey
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Wireless Devices

Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

2016 ◽  
Vol 35 (3) ◽  
Author(s):  
M. Saeed Ansari ◽  
Ali Mahani ◽  
Karim Mohammadi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Design Methodology ◽  
Digital Circuits ◽  
Fault Tolerant ◽  
Sleep Mode ◽  
Clock Generator ◽  
The Third ◽  
Triple Modular Redundancy ◽  
Modular Redundancy

Purpose To increase protection level against transient faults, circuit designers usually take advantage of redundant structures like Triple Modular Redundancy (TMR). Since redundancy compel a significant power overhead, proposing a low power fault tolerant technique in digital circuits is the main objective of this research work. Design/methodology/approach In order to moderate power consumption, we use a dual to triple modular redundancy. In fact, we put one of the modules in a TMR system in sleep mode while the other two operating modules are producing the same outputs. Once a mismatch is detected, the third one exits the sleep mode and the dual modular redundancy (DMR) approach turns into a conventional TMR. Also a novel stoppable clock generator is proposed to handle the sleep mode of the third module. Finally, a new three-input majority voter, compatible with our proposed technique, is presented. Findings Power analysis of combinational circuit benchmarks, ISCAS85, and ISCAS89 as sequential circuit benchmarks are depicted. Simulation results show the power reduction of up to 30% in comparison with the conventional modular redundancy approach. Originality/value Since modular redundancy is the most effective and the most well-known fault tolerant approach which is widely used in reliable circuits designs, it is important to reduce its power consumption. In this paper configuring the sleep mode operation of a circuit and stoppable clock generator lead to a new TMR technique in which the power consumption is strongly reduced.

scholarly journals Various Nano-Scale Technologies: Lower Hardware Complexity of Alu Realizing Utilizing FS-GDI Approach IN 45nm AND 130nm

2021 ◽  
Vol 14 (1) ◽  
pp. 9-34
Author(s):  
Mohsen A. M. El-Bendary ◽  
◽  
M. Ayman ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Delay Time ◽  
Digital Circuits ◽  
Logic Gates ◽  
Propagation Delay ◽  
Hardware Complexity ◽  
Simulation Experiments ◽  
Lower Power ◽  
Full Swing

Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.

Novel Architecture for Low-Power CNTFET-Based Compressors

2019 ◽  
Vol 28 (12) ◽  
pp. 1950207 ◽  
Author(s):  
Morteza Dadashi Gavaber ◽  
Mehrdad Poorhosseini ◽  
Saadat Pourmozafari
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Field Effect Transistors ◽  
Critical Path ◽  
Building Blocks ◽  
Cmos Circuits ◽  
Xor Gate ◽  
Speed Reduction ◽  
Different Types ◽  
Power Delay Product

Carbon nanotube field-effect transistors (CNTFETs) are excellent candidates for the replacement of traditional CMOS circuits. One of the most important modules in many arithmetic circuits is multiplier. Sometimes multipliers may occupy more area as well as consume high power which may cause speed reduction in the critical path. Compressors are important building blocks which are used in most multipliers. In this paper, a low-power architecture is proposed which can be used in compressor designs. The proposed architecture uses a low-power three-input XOR gate to reduce area, delay and power consumption. In order to evaluate the delay and power consumption of circuits, we have used four different types of compressors (3–2, 4–2, 5–2 and 7–2). These four designs were simulated using HSPICE simulation tool with 32-nm CMOS model based on 1-V and 1-GHz frequency operator. The results indicate that the proposed compressor architectures have less power–delay product (PDP) and power consumption in comparison with the existing proposed compressors.

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