scholarly journals Oncurrent-voltage and capacitance-voltage characteristics of metal-semiconductor contacts

2020 ◽  
Vol 44 (4) ◽  
pp. 302-347 ◽  
Author(s):  
Abdulmecit TÜRÜT
Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.


2002 ◽  
Vol 719 ◽  
Author(s):  
Galina Khlyap

AbstractRoom-temperature electric investigations carried out in CO2-laser irradiated ZnCdHgTe epifilms revealed current-voltage and capacitance-voltage dependencies typical for the metal-semiconductor barrier structure. The epilayer surface studies had demonstrated that the cell-like relief has replaced the initial tessellated structure observed on the as-grown samples. The detailed numerical analysis of the experimental measurements and morphological investigations of the film surface showed that the boundaries of the cells formed under the laser irradiation are appeared as the regions of accumulation of derived charged defects of different type of conductivity supplying free charge carriers under the applied electric field.


2003 ◽  
Vol 764 ◽  
Author(s):  
B. Luo ◽  
F. Ren ◽  
M. A. Mastro ◽  
D. Tsvetkov ◽  
A. Pechnikov ◽  
...  

AbstractHigh quality undoped AlGaN/GaN high electron mobility transistors(HEMTs) structures have been gorwn by Hydride Vapor Phase Epitaxy (HVPE). The morphology of the films grown on Al2O3 substrates is excellent with root-mean-square roughness of ∼0.2nm over 10×10μm2 measurement area. Capacitance-voltage measurements show formation of dense sheet of charge at the AlGaN/GaN interface. HEMTs with 1μm gate length fabricated on these structures show transconductances in excess of 110 mS/mm and drain-source current above 0.6A/mm. Gate lag measurements show similar current collapse characteristics to HEMTs fabricated in MBE- or MOCVD grown material.


Author(s):  
LiLung Lai ◽  
Nan Li ◽  
Qi Zhang ◽  
Tim Bao ◽  
Robert Newton

Abstract Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10-1ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.


Author(s):  
Satish Kodali ◽  
Chen Zhe ◽  
Chong Khiam Oh

Abstract Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.


Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.


Author(s):  
Stuart Friedman ◽  
Oskar Amster ◽  
Yongliang Yang ◽  
Fred Stanke

Abstract The use of Atomic Force Microscopy (AFM) electrical measurement modes is a critical tool for the study of semiconductor devices and process development. A relatively new electrical mode, scanning microwave impedance microscopy (sMIM), measures a material’s change in permittivity and conductivity at the scale of an AFM probe tip [1]. sMIM provides the real and imaginary impedance (Re(Z) and Im(Z)) of the probe-sample interface. By measuring the reflected microwave signal as a sample of interest is imaged with an AFM, we can in parallel capture the variations in permittivity and conductivity and, for doped semiconductors, variations in the depletion-layer geometry. An existing technique for characterizing doped semiconductors, scanning capacitance microscopy, modulates the tip-sample bias and detects the tip-sample capacitance with a lock-in amplifier. A previous study compares sMIM to SCM and highlights the additional capabilities of sMIM [2], including examples of nano-scale capacitance-voltage curves. In this paper we focus on the detailed mechanisms and capabilities of the nano-scale C-V curves and the ability to extract semiconductor properties from them. This study includes analytical and finite element modeling of tip bias dependent depletion-layer geometry and impedance. These are compared to experimental results on reference samples for both doped Si and GaN doped staircases to validate the systematic response of the sMIM-C (capacitive) channel to the doping concentration.


Author(s):  
Benedict Drevniok ◽  
St. John Dixon-Warren ◽  
Oskar Amster ◽  
Stuart L Friedman ◽  
Yongliang Yang

Abstract Scanning microwave impedance microscopy was used to analyze a CMOS image sensor sample to reveal details of the dopant profiling in planar and cross-sectional samples. Sitespecific capacitance-voltage spectroscopy was performed on different regions of the samples.


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