The Design of Sound and Light Controlled Corridor LED Lamp Based on Double Integration Detection

2013 ◽  
Vol 347-350 ◽  
pp. 93-97
Author(s):  
Xiu Lei Cui ◽  
Yong Gao Jin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Sensitivity ◽  
Current Drive ◽  
Constant Current ◽  
Detection Accuracy ◽  
Double Integration ◽  
Detection Circuit ◽  
Micro Power ◽  
Operation Stability

The design of a high-sensitivity LED lamp with low standby consumption, sound and light controlled type based on the micro-power consumption characteristic of MK6A12P is presented in this paper. The standby power consumption is less than 0.07W. And the problem of the light sense unit influenced by the change of the supply voltage is solved by the design of double integration detection circuit, thereby, the detection accuracy of brightness is improved. The service life of LED lamp is greatly prolonged with constant current drive. It is proved by the experiment that the LED lamp has the advantages of simple circuit structure, high operation stability and high cost performance.

scholarly journals Power-Based Non-Intrusive Condition Monitoring for Terminal Device in Smart Grid

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3635 ◽  
Author(s):  
Guoming Zhang ◽  
Xiaoyu Ji ◽  
Yanjie Li ◽  
Wenyuan Xu
Keyword(s):  
Smart Grid ◽  
Power Consumption ◽  
Real Time ◽  
Condition Monitoring ◽  
Resource Constraints ◽  
Detection System ◽  
Stable Operation ◽  
Detection Accuracy ◽  
Monitoring Method ◽  
Dsp Processors

As a critical component in the smart grid, the Distribution Terminal Unit (DTU) dynamically adjusts the running status of the entire smart grid based on the collected electrical parameters to ensure the safe and stable operation of the smart grid. However, as a real-time embedded device, DTU has not only resource constraints but also specific requirements on real-time performance, thus, the traditional anomaly detection method cannot be deployed. To detect the tamper of the program running on DTU, we proposed a power-based non-intrusive condition monitoring method that collects and analyzes the power consumption of DTU using power sensors and machine learning (ML) techniques, the feasibility of this approach is that the power consumption is closely related to the executing code in CPUs, that is when the execution code is tampered with, the power consumption changes accordingly. To validate this idea, we set up a testbed based on DTU and simulated four types of imperceptible attacks that change the code running in ARM and DSP processors, respectively. We generate representative features and select lightweight ML algorithms to detect these attacks. We finally implemented the detection system on the windows and ubuntu platform and validated its effectiveness. The results show that the detection accuracy is up to 99.98% in a non-intrusive and lightweight way.

scholarly journals A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1078
Author(s):  
Thi Thuy Pham ◽  
Dongmin Kim ◽  
Seo-Hyeong Jeong ◽  
Junghyup Lee ◽  
Donggu Im
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Supply Voltage ◽  
Current Source ◽  
Low Noise ◽  
The Body ◽  
Common Source ◽  
Conversion Gain ◽  
Input Transistor ◽  
Envelope Detector

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

CMOS PULSE GENERATOR FOR BPSK, OOK, PAM, AND PPM MODULATIONS

2009 ◽  
Vol 18 (03) ◽  
pp. 487-495 ◽  
Author(s):  
VINCENZO STORNELLI ◽  
GIUSEPPE FERRI ◽  
KING PACE
Keyword(s):  
Remote Control ◽  
Power Consumption ◽  
Pulse Duration ◽  
Short Range ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Pulse Repetition Frequency ◽  
Cmos Technology ◽  
Single Chip ◽  
Control Applications

This work presents a single chip integrated pulse generator-modulator to be utilized in a short range wireless radio sensors remote control applications. The circuit, which can generate single pulses, modulated in BPSK, OOK, PAM, and also PPM, has been developed in a standard CMOS technology (AMS 0.35 μm). Typical pulse duration is about 1 ns while pulse repetition frequency is until 200 MHz (5 ns "chip" time). The operating supply voltage is ± 2.5 V, while the whole power consumption is about 15 mW. Post-layout parametric and corner analyses have confirmed the theoretical expectations.

scholarly journals A Novel Differential Log-Companding Amplifier for Biosignal Sensing

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Zigang Dong ◽  
Xiaolin Zhou ◽  
Yuanting Zhang
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Nonlinear Function ◽  
New Method ◽  
Total Power ◽  
Maximum Output ◽  
Output Current ◽  
Current Range ◽  
Symmetrical Configuration ◽  
Total Power Consumption

We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18 μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is166.1 fA/Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

scholarly journals ECL-Based SiC Logic Circuits for Extreme Temperatures

2015 ◽  
Vol 821-823 ◽  
pp. 910-913 ◽  
Author(s):  
Luigia Lanni ◽  
Bengt Gunnar Malm ◽  
Mikael Östling ◽  
Carl Mikael Zetterling
Keyword(s):  
Power Consumption ◽  
Oscillation Frequency ◽  
Digital Circuits ◽  
Supply Voltage ◽  
Logic Circuits ◽  
Ring Oscillator ◽  
Extreme Temperatures ◽  
Temperature Range ◽  
Stable Noise ◽  
Gate Design

Integrated digital circuits, fabricated in a bipolar SiC technology, have been successfully tested up to 600 °C. Operated with-15 V supply voltage from 27 up to 600 °C OR-NOR gates exhibit stable noise margins of about 1 or 1.5 V depending on the gate design, and increasing delay-power consumption product in the range 100 - 200 nJ. In the same temperature range an oscillation frequency of about 1 MHz is also reported for an 11-stage ring oscillator.

Smart Battery Charging Station for ElectricVehicle Using Half Bridge Power Converter

2018 ◽  
Vol 19 (4) ◽  
Author(s):  
B. R. Ananthapadmanabha ◽  
Rakesh Maurya ◽  
Sabha Raj Arya ◽  
B. Chitti Babu
Keyword(s):  
Power Quality ◽  
Distribution System ◽  
Reactive Power ◽  
Supply Voltage ◽  
Power Converter ◽  
Constant Current ◽  
Battery Charging ◽  
Charging Station ◽  
Simulink Model ◽  
Smart Charging

Abstract This paper presents a concept of smart charging station using bidirectional half bridge converter for an electric vehicle. This battery charging station is useful for charging applications along with harmonics and reactive power compensation in a distribution system. A filter which is adaptive to the supply voltage frequency is used for the estimation of the 50 Hz component of load current. Due to additional features of vehicle charger, associated with the power quality improvement, there will be a drastic reduction in the current drawn from utility to meet the same load demand. The charging station presented in this paper is termed as smart with several function. The proposed smart charger is able to improve power quality of residential loads or other loads, not only during charging/discharging of the vehicle battery, but also in the absence of the vehicle. The Simulink model is developed with MATLAB software and its simulation results are presented. The level of current distortion during charging and and discharging mode is recorded 1.6 % and 2.4 % respectively with unity supply power factor during experiments. The performance of converter is evaluated during charging modes both in constant current (CC) and constant voltage (CV) modes.

Micro-Power Wireless CSMA/CA Algorithm Improvement and Simulation Based on the Electric Power Business

2014 ◽  
Vol 494-495 ◽  
pp. 1640-1646
Author(s):  
Yu Lan ◽  
Xin Lu ◽  
Ye Shen He ◽  
Yun Feng Li
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Collision Detection ◽  
Wireless Transmission ◽  
Low Power Consumption ◽  
Mac Layer ◽  
Electric System ◽  
Simulation Based ◽  
Micro Power ◽  
Fixed Power

In the micro-power wireless transmission of the electric system, positions among modes are relatively fixed, power business data is reported at specific time points, and time distribution presents great differences. Key technologies of IEEE802.15.4 MAC layer protocol is expounded, shortages of collision detection and CSMA/CA on power business support, etc. are discussed, self-adaptive low-power consumption CSMA/CA algorithm which is more suitable for business of the electric system are designed and improved, and the algorithm goes through simulation experiment against the business characteristics of micro-power wireless network of the electric system. The simulation result demonstrates the algorithm may be greatly adapted to changes of network traffic under a relatively fixed environment of network topology on the premise of low power consumption.

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