SPATIAL WAVEFUNCTION-SWITCHED (SWS)-FET: A NOVEL DEVICE TO PROCESS MULTIPLE BITS SIMULTANEOUSLY WITH SUB-PICOSECOND DELAYS

2011 ◽  
Vol 20 (03) ◽  
pp. 641-652 ◽  
Author(s):  
F. C. JAIN ◽  
J. CHANDY ◽  
B. MILLER ◽  
E-S. HASANEEN ◽  
E. HELLER
Keyword(s):  
Quantum Wells ◽  
Field Effect Transistors ◽  
Logic Gates ◽  
Spatial Location ◽  
Full Adder ◽  
Channel Length ◽  
Coupled Quantum Wells ◽  
Quantum Well Structures ◽  
Novel Device ◽  
Capacitance Voltage

Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs - AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n -channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.

Novel Multiplexer Design Using Multi-State Spatial Wavefunction-Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1520011 ◽  
Author(s):  
Pial Mirdha ◽  
Murali Lingalugari ◽  
Evan K. Heller ◽  
John A. Chandy ◽  
Faquir C. Jain
Keyword(s):  
Quantum Wells ◽  
Gate Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Logic Device ◽  
Coupled Quantum Wells ◽  
Conduction Mode

In this paper, we propose a multiplexer design based on use of a twin channel and twin drain spatial wavefunction-switched field-effect transistors (SWSFETs). SWSFET comprises of vertically stacked coupled quantum wells devices, which are the channels, where depending on the gate voltage only one of the channels is in conduction mode. Using SWSFET in multi-channel and single drain configuration operates as a multi-valued logic device. 2:1 and 4:2 multiplexer designs are proposed which are compatible with current CMOS technology and with all SWSFET. Both designs lead to greater than 4X reduction in transistor count. Ngspice simulation of circuits is also presented.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550008 ◽  
Author(s):  
Bander Saman ◽  
P. Mirdha ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. C. Jain ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Behavioral Model ◽  
Charge Carrier Concentration ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Proposed Model ◽  
High Band

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

QUANTUM DEVICES WITH MULTIPOLE-ELECTRODE — HETEROJUNCTIONS HYBRID STRUCTURES

2002 ◽  
Vol 12 (04) ◽  
pp. 1159-1171
Author(s):  
RAPHAEL TSU
Keyword(s):  
Quantum Wells ◽  
Quantum Confinement ◽  
Field Effect Transistors ◽  
Inversion Layer ◽  
Quantum Hall ◽  
Hybrid Structure ◽  
Hybrid Structures ◽  
Double Gate ◽  
Quantum Devices ◽  
Quantum Well Structures

Since the introduction of the man-made superlattices and quantum well structures, the field has taken off and developed into Quantum Slab, QS; Quantum Wire, QW; Quantum Dot, QD; and Nanoelectronics. This rapidly expanding field owes its success to the development of epitaxially grown heterojunctions and heterostructures to confine carriers in injection lasers. Meanwhile, the advancement of lithography allows potentials to be applied in nanoscale dimension leading to the possibility of quantum confinement without heterostructures. Actually, quantum states in the inversion layer of field effect transistors, FETs, formed by the application of a large gate voltage appeared several years before the introduction of the superlattices and quantum wells. The quantum Hall effect was first discovered in the Si inversion layer. This chapter, Multipole-Electrode Heterojunction Hybrid Structure, MEHHS, discusses hybrid structures of heterojunctions and applied potentials via multipole-electrodes for a much wider variety of structures for future quantum devices. The technology required to fabricate these electrodes, to some degree, is routinely used in the double-gate devices. Few specific examples are detailed here, hopefully, to stimulate a rapid adoption of a hybrid system for the formation of quasi-discrete states for quantum devices.

Quantum Confinement Stark Effect of Different Gainnas Quantum Well Structures

2013 ◽  
Vol 773 ◽  
pp. 622-627
Author(s):  
Ying Ning Qiu ◽  
Wei Sheng Lu ◽  
Stephane Calvez
Keyword(s):  
Electric Field ◽  
Quantum Well ◽  
Quantum Wells ◽  
External Electric Field ◽  
Quantum Confinement ◽  
Stark Effect ◽  
Band Gap Energy ◽  
Electron Effective Mass ◽  
Coupled Quantum Wells ◽  
Quantum Well Structures

The quantum confinement Stark effect of three types of GaInNAs quantum wells, namely single square quantum well, stepped quantum wells and coupled quantum wells, is investigated using the band anti-crossing model. The comparison between experimental observation and modeling result validate the modeling process. The effects of the external electric field and localized N states on the quantized energy shifts of these three structures are compared and analyzed. The external electric field applied to the QW not only changes the potential profile but also modulates the localized N states, which causes band gap energy shifts and increase of electron effective mass.

Designing and Modeling of Logic Circuits Based on Switching of the Gated Oligo-Phenylenevinylene Molecule

2017 ◽  
Vol 46 ◽  
pp. 82-92 ◽  
Author(s):  
Saleh Safapour ◽  
Reza Sabbaghi-Nadooshan ◽  
Ali Asghar Shokri
Keyword(s):  
Molecular Electronics ◽  
Field Effect Transistors ◽  
Circuit Simulation ◽  
Logic Gates ◽  
Full Adder ◽  
Logic Circuits ◽  
Simulation Software ◽  
Molecular Systems ◽  
Half Adder ◽  
The Cost

Molecular electronics seeks to decrease the cost, power consumption and size of devices, using a variety of approaches. However, few attempts have been made to address circuit simulation. The availability of common semiconductor components means they can be used for modeling and simulating molecular circuits to speed progress in molecular electronics. The present study examines the switching of a gated oligo-phenylenevinylene (OPV) molecule as a NMOS molecular transistor, resistance as an indicator of methyl molecules, and the linking of these abilities using LTspice simulation software. The circuit simulation of molecules of basic logic gates, half-adder, full-adder, and multiplier logic circuits are carried out. The numerical results may shed light on the next applications of molecular systems and make them a good, promising candidate for field-effect transistors.

Theory of Light-Induced Drift of Electrons in Coupled Quantum Wells

1992 ◽  
Author(s):  
Mark I. Stockman ◽  
Leonid S. Muratov ◽  
Thomas F. George
Keyword(s):  
Quantum Wells ◽  
Coupled Quantum Wells

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

scholarly journals Modelling of Dynamic Properties of Silicon Carbide Junction Field-Effect Transistors (JFETs)

Energies ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 187 ◽  
Author(s):  
Kamil Bargieł ◽  
Damian Bisewski ◽  
Janusz Zarębski
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuit ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Dynamic Properties ◽  
Modified Model ◽  
Spice Model ◽  
Capacitance Voltage ◽  
Effect Transistor ◽  
Switching Characteristics

The paper deals with the problem of modelling and analyzing the dynamic properties of a Junction Field Effect Transistor (JFET) made of silicon carbide. An examination of the usefulness of the built-in JFET Simulation Program with Integrated Circuit Emphasis (SPICE) model was performed. A modified model of silicon carbide JFET was proposed to increase modelling accuracy. An evaluation of the accuracy of the modified model was performed by comparison of the measured and calculated capacitance–voltage characteristics as well as the switching characteristics of JFETs.

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