Electrical Characteristics of Different Gate Geometry of FinFET

2016 ◽  
Vol 705 ◽  
pp. 174-178 ◽  
Author(s):  
Nuttapong Patcharasardtra ◽  
Weera Pengchan
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Electrical Characteristics ◽  
Gate Width ◽  
Voltage Threshold ◽  
Gate Structure ◽  
Current Voltage

This paper proposed to the electrical characteristics of difference gate geometry of FinFET. Four of difference gate structure have been designed and simulated by GTS Framework TCAD software which is simulation the characteristics of FinFET device include drain current-voltage, threshold voltage and subthreshold swing. Then, the electrical characteristics was compared. From the result found that the drain current depend on gate geometry of FinFET. The largest gate geometry of FinFET device was the rectangle shape with gate width at 66 nm, IDS about 19.8 mA and VTH = 0.5 V and the smallest gate geometry, the triangle shape with gate width at 52 nm and give IDS about 8.5 mA and Vth = 0.5 V.

Development of 1200 V, 3.7 mΩ-cm2 4H-SiC DMOSFETs for Advanced Power Applications

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Voltage Drop ◽  
Drain Current ◽  
Subthreshold Swing ◽  
Active Area ◽  
Gate Bias ◽  
Forward Voltage ◽  
Recent Developments ◽  
Forward Voltage Drop

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Analysis of electrical characteristics and electroluminescent efficiency of field induced contact-DGOLET

2022 ◽  
pp. 1-11
Author(s):  
Sandeep Kumar Ojha ◽  
Brijesh Kumar
Keyword(s):  
Threshold Voltage ◽  
Dynamic Control ◽  
Drain Current ◽  
Vital Role ◽  
Electrical Characteristics ◽  
Flexible Display ◽  
Light Emitting ◽  
Device Architecture ◽  
Dual Gate ◽  
Current Densities

This research paper discusses the significance development in field-induced contact dual-gate organic light emitting transistor (FIC-DGOLET) device architecture and characteristics. The device behaviour is analyzed and observed significant value of electroluminescent efficiency. The deep investigation of FIC-DGOLET device is discussed in this paper, where impact of varying the various parameters such as thickness of organic semiconductor (OSC) materials from the range of 400 nm to 200 nm at altered value of threshold voltage by using 2D ATLAS simulator. Its theoretical calculation influence over the dynamic control of the device characteristics such as saturated drain current (I ds ), mobility (μ), threshold voltage (V th ) as well as sub threshold swing. The FIC-DGOLET is a dual-gate transistor which also emits light by the operations of two accumulated regions, that are electrons and holes which is not completely overlapped to each other. The leakage current in DG-OLET can be reduced to the extent that 70% than single gate OLET (SG-OLET). The recombination zone mechanism of FIC-DGOLET plays a vital role in its performance, where we get comparable value of electroluminescent efficiency with reported, low value of exciton quenching and current densities. The extracted parameters of DG-OLETs are like drive current of 100A, I on/off 108, threshold voltage V th of 1.3 V at V gs of –3 V and V ds of 0 to –3 V. These extracted performance parameters are very helpful in designing of flexible display applications.

Electrical Instabilities and 1/f Noise in Organic Pentacene Thin Film Transistors

2000 ◽  
Vol 660 ◽  
Author(s):  
P. V. Necliudov ◽  
M. Shur ◽  
D. J. Gundlach ◽  
T. N. Jackson
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Electrical Characteristics ◽  
Threshold Voltage Shift ◽  
Current Voltage ◽  
Noise Measurements ◽  
Current Voltage Characteristics ◽  
Amorphous Si ◽  
Bias Temperature Stress

ABSTRACTWe report on the influence of Bias-Temperature Stress (BTS) on the pentacene Thin Film Transistors (TFTs) electrical characteristics and on their 1/f noise level. The gate BTS primarily affects the TFT threshold voltage, leaving both mobility and sub-threshold slope values almost unchanged. The degree of the threshold voltage shift induced by the positive or negative BTS depends on the TFT design and the BTS parameters. The current-voltage characteristics time dependence of the organic TFTs, subjected to the BTS, resembles that for amorphous-Si TFTs. The results of the 1/f noise measurements in the organic TFTs allowed us to conclude that the gate BTS primarily affects the TFT contact regions, resulting in the increase of both the contact noise and the contact resistance.

Comparison of the Threshold-Voltage Stability of SiC MOSFETs with Thermally Grown and Deposited Gate Oxides

2010 ◽  
Vol 645-648 ◽  
pp. 681-684 ◽  
Author(s):  
Michael Grieb ◽  
Masato Noborio ◽  
Dethard Peters ◽  
Anton J. Bauer ◽  
Peter Friedrichs ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Drain Current ◽  
Gate Oxide ◽  
Electrical Characteristics ◽  
Gate Oxides ◽  
Operation Conditions ◽  
Mos Devices ◽  
Thermal Oxide ◽  
Order Of Magnitude

The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.

Improved On-Current of 4H-SiC MOSFETs with a Three-Dimensional Gate Structure

2009 ◽  
Vol 615-617 ◽  
pp. 753-756
Author(s):  
Yuichiro Nanen ◽  
Hironori Yoshioka ◽  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Three Dimensional ◽  
Side Wall ◽  
Chemical Vapor ◽  
Drain Current ◽  
Gate Oxide ◽  
Ion Etching ◽  
Gate Width ◽  
Gate Structure

4H-SiC (0001) MOSFETs with a three-dimensional gate structure, which has a top channel on the (0001) face and side-wall channels on the {11-20} face have been fabricated. The three-dimensional gate structures with a 1-5 m width and 0.8 m height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300°C. The fabricated MOSFETs have exhibited superior characteristics: ION / IOFF, the subthreshold swing and VTH are 1010, 250 mV/decade and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1 m-wide MOSFET is ten times higher than that of a conventional planar MOSFET.

DC Characteristics of AlGaN/GaN HEMTs Using a Dual-Gate Structure

2015 ◽  
Vol 15 (10) ◽  
pp. 7467-7471 ◽  
Author(s):  
Sejun Hong ◽  
Abu ul Hassan Sarwar Rana ◽  
Jun-Woo Heo ◽  
Hyun-Seok Kim
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
High Electron Mobility Transistors ◽  
High Electron ◽  
Positive Direction ◽  
Electron Mobility Transistors ◽  
Gate Structure ◽  
Dual Gate ◽  
Gan Hemts ◽  
Dimensional Electron Gas

Multiple techniques such as fluoride-based plasma treatment, a p-GaN or p-AlGaN gate contact, and a recessed gate structure have been employed to modulate the threshold voltage of AlGaN/GaN-based high-electron-mobility transistors (HEMTs). In this study, we present dual-gate AlGaN/GaN HEMTs grown on a Si substrate, which effectively shift the threshold voltage in the positive direction. Experimental data show that the threshold voltage is shifted from −4.2 V in a conventional single-gate HEMT to −2.8 V in dual-gate HEMTs. It is evident that a second gate helps improve the threshold voltage by reducing the two-dimensional electron gas density in the channel. Furthermore, the maximum drain current, maximum transconductance, and breakdown voltage values of a single-gate device are not significantly different from those of a dual-gate device. For the fabricated single- and dual-gate devices, the values of the maximum drain current are 430 mA/mm and 428 mA/mm, respectively, whereas the values of the maximum transconductance are 83 mS/mm and 75 mS/mm, respectively.

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

2021 ◽  
Vol 14 (1) ◽  
pp. 014003
Author(s):  
Shahab Mollah ◽  
Kamal Hussain ◽  
Abdullah Mamun ◽  
Mikhail Gaevski ◽  
Grigory Simin ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
High Current ◽  
Enhancement Mode ◽  
Recessed Gate

scholarly journals Study and Assessment of Defect and Trap Effects on the Current Capabilities of a 4H-SiC-Based Power MOSFET

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 735
Author(s):  
Fortunato Pezzimenti ◽  
Hichem Bencherif ◽  
Giuseppe De Martino ◽  
Lakhdar Dehimi ◽  
Riccardo Carotenuto ◽  
...  
Keyword(s):  
Drain Current ◽  
Oxide Semiconductor ◽  
Temperature Dependent ◽  
Channel Mobility ◽  
Blocking Voltage ◽  
Current Voltage ◽  
Wide Range ◽  
Temperature Ranges ◽  
Joint Contribution ◽  
State Resistance

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.

Preparation and Electrical Characteristics of (100), (111), and Randomly Oriented PZT Thin Films

1994 ◽  
Vol 361 ◽  
Author(s):  
Chang Jung Kim ◽  
Dae Sung Yoon ◽  
Joon Sung Lee ◽  
Chaun Gi Choi ◽  
Won Jong Lee ◽  
...  
Keyword(s):  
Thin Films ◽  
Sol Gel ◽  
Hysteresis Loops ◽  
Test System ◽  
Electrical Characteristics ◽  
Pzt Thin Films ◽  
Pole Figures ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Drying Conditions

ABSTRACTThe (100), (111) and randomly oriented PZT thin films were fabricated on Pt/Ti/Coming 7059 glass using sol-gel method. The thin films having different orientation were fabricated by different drying conditions for pyrolysis. The preferred orientations of the PZT thin films were observed using XRD, rocking curves, and pole figures. The microstructures were investigated using SEM. The hysteresis loops and capacitance-voltage characteristics of the films were investigated using a standardized ferroelectric test system. The dielectric constant and current-voltage characteristics of the films were investigated using an impedance analyzer and pA meter, respectively. The films oriented in a particular direction showed superior electrical characteristics to the randomly oriented films.

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