Unique Size-Dependent Challenges for BEOL Cleans in the Patterning of Sub-20 nm Features

2012 ◽  
Vol 195 ◽  
pp. 103-106 ◽  
Author(s):  
Kanwal Jit Singh
Keyword(s):  
Beam Theory ◽  
Dielectric Materials ◽  
Material Strength ◽  
K Value ◽  
Root Cause ◽  
Size Dependent ◽  
Performance Requirements ◽  
Black Boxes ◽  
20 Nm ◽  
Low K

BEOL Cleans has been and continues to be one of the most mysterious black boxes of semiconductor manufacturing. It has the unenviable task of removing post-plasma processing polymer residues, being compatible with ultra low-k dielectric materials that continue to scale k-value at the expense of material strength, and ensuring that any formulation that accomplishes the above objectives is also compatible with Cu and all other metals on the wafer used for liners or caps. In order to meet the performance requirements of next generation devices, Moore's law mandates continued scaling of dimensions with the additional challenges of size-dependent complexities for BEOL cleans development. Patterning of sub-20 nm features on thin ILD stacks suffers from the problems of etch-induced line undulation [1, 2] and cleans-induced pattern collapse [3]. High aspect ratio's, non-uniform drying, surface tension and low material strength have all been implicated as the root cause for pattern collapse during cleans [4]. Classical equations used to describe pattern collapse for resist lines that rely on 2D beam theory and finite element modeling [5] are not as applicable to patterned low-k dielectrics because material changes such as sidewall polymer residues, lowering of Young's modulus and changing pattern densities present different solid surfaces with widely varying wettability and diffusivity parameters [6, .

Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

2017 ◽  
Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Dielectric Films ◽  
Planar Surface ◽  
Chemical Methods ◽  
Root Cause ◽  
Essential Step ◽  
Dielectric Layers ◽  
Wet Chemical ◽  
20 Nm ◽  
Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

Optimization of Dielectric Cap Adhesion to Ultra-Low-k Dielectrics

2004 ◽  
Vol 812 ◽  
Author(s):  
Greg Spencer ◽  
Alfred Soyemi ◽  
Kurt Junker ◽  
Jason Vires ◽  
Michael Turner ◽  
...  
Keyword(s):  
Adhesion Strength ◽  
Dielectric Materials ◽  
Substantial Improvement ◽  
Film Deposition ◽  
Interface Adhesion ◽  
K Value ◽  
Layer Film ◽  
Point Bend ◽  
Low K ◽  
Deposition Conditions

AbstractIn this work, the adhesion of CVD dielectric caps to ULK MSQ spin-on dielectric materials with k values of 2.2 and 2.0, and a ULK CVD material with a k value of 2.7 is presented. A substantial improvement in cap adhesion to both the k2.2 ULK MSQ and the k2.7 ULK CVD material is demonstrated. The improvement is obtained using a low-k CVD glue material between the ULK dielectric and the subsequent cap material and/or by optimizing the CVD cap film deposition. Four-point bend measurement of adhesion strength is used to quantify the improvement in interface adhesion. The improvement in CVD cap adhesion is demonstrated to be strongly dependent upon both the glue layer film and the cap deposition conditions. While optimization of the CVD cap materials results in adequate adhesion for the k2.2 ULK MSQ, these improvements are demonstrated not to extend to the k2.0 ULK MSQ film.

Use of Nanoindentation to Characterise the Plasma Damage Region in Low-k Dielectric Films

2006 ◽  
Author(s):  
Jon M. Molina-Aldareguia ◽  
Maria R. Elizalde ◽  
Ibon Ocan˜a ◽  
Javier Gil-Sevillano ◽  
Jose´ M. Marti´nez-Esnaola ◽  
...  
Keyword(s):  
Mechanical Properties ◽  
Depth Resolution ◽  
Dielectric Materials ◽  
Dynamical Response ◽  
Indentation Modulus ◽  
Depth Sensing ◽  
K Value ◽  
Graded Structure ◽  
Graded Structures ◽  
Low K

The thermo-mechanical robustness of interconnect structures is a key reliability concern for integrated circuits. The introduction of new low dielectric constant (low-k) materials with deteriorated mechanical strength (i.e., Young Modulus decreases exponentially with film porosity, which is needed to lower the k value of the dielectric materials) to meet the RC delay goals increase the risk of mechanical adhesive and/or cohesive failure of the device during packaging or even in service. Therefore, the mechanical properties of low-k dielectrics must be studied in detail. This is made very challenging by the fact that they have submicron thickness and that they often display a graded structure due to the damage introduced by exposure to different plasmas during processing. In this context, we demonstrate that nanoindentation is very well suited to study this type of materials. We will show how conventional depth sensing nanoindentation is of limited value to characterise the extent of the plasma induced damage because this extents just a few tens of nanometres and the graded structure can not be sampled with enough depth resolution. However, nanoindentation in modulus mapping mode can achieve enough depth resolution to characterise such nanoscale graded structures. In this technique, the electrostatic force acting on the indenter tip is sinusoidally modulated, while contact mode imaging at a very small force is performed. The dynamical response is then analyzed to extract the local indentation modulus of the sample at each pixel. By using this technique, we have depth profiled the mechanical properties of the plasma induced damage region of OSG films exposed to different plasmas, by acquiring modulus maps as a function of thickness removed in wear experiments. The results correlate well with the density depth profiles derived from X-Ray Reflectivity measurements.

Pore sealing of SiOCH ultra low-k dielectrics with polyimide Langmuir-Blodgett film

2012 ◽  
Vol 1428 ◽  
Author(s):  
S.I. Goloudina ◽  
A. S. Ivanov ◽  
M. B. Krishtab ◽  
V.V. Luchinin ◽  
V.M. Pasyuta ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Deposition Process ◽  
Dielectric Materials ◽  
K Value ◽  
Langmuir Blodgett ◽  
Air Interface ◽  
Pore Sealing ◽  
Materials Used ◽  
High Dielectric ◽  
Low K

ABSTRACTContinuous decrease of the feature size of transistors in modern integrated circuits (ICs) constrains thickness of auxiliary dielectric layers in interconnects because of their relatively high dielectric constant, which reduces the efficiency of low-k material integration. Dielectric materials used today as barrier or etch-stop layers are usually SiN (k ∼ 7.0) and SiCN (k ∼ 4.8), which k-value significantly exceeds that of recent ultra low-k materials (k < 2.2). In our work we have investigated thin films of rigid-chain polyimide (PI) with a k-value of about 3.2-3.3. This film was deposited using a Langmuir-Blodgett (LB) technique and can be as thin as several monolayers. The intermolecular interaction of densely packed precursor macromolecules within a monolayer formed at the water-air interface makes it possible to avoid penetration of precursor material inside the pores. The latter peculiarity of the deposition process results in a pore sealing effect using a 4 nm PI film.

Process Flow Employed for Parametric Test Structure Shorts Fault Isolation in 20 nm and Sub-20 nm Technologies in High Throughput Foundries

2017 ◽  
Author(s):  
Satish Kodali ◽  
Mia Nasimullah ◽  
Yuting Wei ◽  
Chong Khiam Oh ◽  
Felix Beaudoin
Keyword(s):  
Process Development ◽  
Fault Isolation ◽  
Predominant Role ◽  
Process Flow ◽  
Parametric Test ◽  
Root Cause ◽  
Development Cycle ◽  
Root Cause Identification ◽  
20 Nm ◽  
Low K

Abstract With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.

A Study on Reduced/Absent Adhesion/Cap Layers for Optimized BEOL RC Performance

2019 ◽  
Vol 2019 (1) ◽  
pp. 000591-000594
Author(s):  
Dewei Xu ◽  
Zhiguo Sun ◽  
Haojun Zhang ◽  
Scott Pozder ◽  
Patrick Justison ◽  
...  
Keyword(s):  
Adhesion Strength ◽  
Interfacial Adhesion ◽  
Dielectric Materials ◽  
Advanced Technology ◽  
Integration Scheme ◽  
K Value ◽  
Carbon Doped ◽  
Technology Node ◽  
Interfacial Adhesion Strength ◽  
Low K

Abstract Lower RC delay is vital to achieve optimal and competitive circuit performance and hence drives the endlessly pursued BEOL integration scheme advancement. To date low-k dielectric materials, i.e., fluorine-doped oxides, carbon-doped oxide (SiCOH), to porous carbon-doped oxides (p-SiCOH) have been implemented. However, due to the process integration challenges with inherently weak low-k materials, the trend to pursue lower k dielectrics has come to a plateau as technology nodes scale down past 20/14nm. On the other hand, the trend of geometry layer thickness shrinking down, such as trench CD and height, via CD and height, etc., still continues for each advanced technology node. In the BEOL stack adhesion layers (oxide + gradient layers) (ALs) with higher k value were introduced to enhance interface adhesion strength between SiCOH/p-SiCOH and dielectric cap film (SiCN), which offset the intrinsic RC benefit from low-k dielectric material. At more advanced nodes and beyond, the combined ALs and cap film could be up to via or trench height, which poses a huge challenge to meet desired RC performance and technology node scaling. Therefore, the thickness reduction of ALs and cap film becomes necessary for further technology node scaling. In this study, samples with interfacial full ALs, reduced ALs and bulk only (no ALs) for p-SiCOH (k=2.75) on various cap films were prepared, such as SiCN, SiCN/ODC, SiCN/AlONx, etc. TOF-SIMS analyses was used to confirm the composition of the dielectric stacks and later check the debonded surface morphology. Four-point bend adhesion tests were conducted to evaluate interfacial adhesion strength. Results show the interfacial adhesion strength on samples with reduced Als and bulk only (no ALs) is dropped by ~20% and ~30%, respectively. Additional ODC layer on top of SiCN would increase the interfacial adhesion strength by ~10%. It is suggested that reduced ALs may be adequate to satisfy overall CPI requirement for the BEOL integration scheme of p-SiCOH on advanced dielectric cap films (AlN + ODC). The coupling capacitance reduction for a combined reduced ALs and advanced dielectric cap can be up to 16% at M0 level and 10% at Mx level for a 40nm metal pitch.

Effect of Colloidal Silica as Abrasive on Low-k Dielectric Materials in Chemical Mechanical Planarization

2012 ◽  
Vol 455-456 ◽  
pp. 1149-1152
Author(s):  
Yan Gang He ◽  
Jia Xi Wang ◽  
Xiao Wei Gan ◽  
Wei Juan Li ◽  
Yu Ling Liu
Keyword(s):  
Surface Quality ◽  
Colloidal Silica ◽  
Chemical Mechanical Planarization ◽  
Dielectric Materials ◽  
Critical Surface ◽  
K Value ◽  
Quality Issue ◽  
Similar Range ◽  
Low K

With low-k dielectric materials taking the place of oxide dielectrics as the primary dielectric materials, the low-k dielectric materials and interconnection Cu metals during Chemical Mechanical Planarization (CMP) is becoming a critical surface quality issue as well. In this study, experiments are carefully designed and conducted to investigate the effects of colloidal silica under compared acidic slurry and self-prepared alkaline slurry on k value of low-k dielectric materials, and in both of the slurry, colloidal silica (20~30nm) was used as polishing abrasive. The results showed that k value of low-k dielectric materials both increased within a similar range (self-prepared alkaline slurry, 3.27~3.33; commercial acidic slurry, 3.26~3.32), however, the results showed a obviously different result from reference’s report.

Studies of the Coefficient of Thermal Expansion of Low-k ILD Materials by X-Ray Reflectivity

2006 ◽  
Vol 914 ◽  
Author(s):  
George Andrew Antonelli ◽  
Tran M. Phung ◽  
Clay D. Mortensen ◽  
David Johnson ◽  
Michael D. Goodner ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Expansion ◽  
Coefficient Of Thermal Expansion ◽  
Chemical Vapor ◽  
Dielectric Materials ◽  
Free Standing ◽  
Dielectric Thin Films ◽  
X Ray ◽  
Chemical Vapor Deposited ◽  
Low K

AbstractThe electrical and mechanical properties of low-k dielectric materials have received a great deal of attention in recent years; however, measurements of thermal properties such as the coefficient of thermal expansion remain minimal. This absence of data is due in part to the limited number of experimental techniques capable of measuring this parameter. Even when data does exist, it has generally not been collected on samples of a thickness relevant to current and future integrated processes. We present a procedure for using x-ray reflectivity to measure the coefficient of thermal expansion of sub-micron dielectric thin films. In particular, we elucidate the thin film mechanics required to extract this parameter for a supported film as opposed to a free-standing film. Results of measurements for a series of plasma-enhanced chemical vapor deposited and spin-on low-k dielectric thin films will be provided and compared.

Via Cleaning Technology for Post Etch Residues

2005 ◽  
Vol 103-104 ◽  
pp. 357-360
Author(s):  
B.G. Sharma ◽  
Chris Prindle
Keyword(s):  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Copper Interconnects ◽  
Limiting Factor ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Widespread Acceptance ◽  
Cleaning Technology ◽  
Rc Delay ◽  
Low K

Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.

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