Advanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-36 ◽  
Author(s):  
Elvino Da Silveira ◽  
Keith Best ◽  
Gurvinder Singh ◽  
Roger McCleary
Keyword(s):  
Cost Reduction ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Main Driver ◽  
Ratio Imaging ◽  
Advanced Packaging ◽  
High Yields ◽  
Line Space

For more than 50 years the semiconductor industry has pursued Moore's law, continuously improving device performance, reducing cost, and scaling transistor geometries down to where advanced CMOS has reached beyond the 10nm technology node. The commensurate increase in I/O count has created many challenges for device packaging which hitherto was considered low cost with simple solutions. It was once thought that old backend foundry lithography steppers could be used to address the new packaging requirements; which was true whilst the substrates remained in the traditional 300mm Silicon format. The recent unprecedented rapid growth in Fan Out Wafer Level Packaging (FOWLP) applications has introduced a more complicated landscape of process challenges, with no restriction on substrate format, where cost is the main driver and high yields are mandatory. This paper discusses the lithography process challenges that have ensued from disruptive FOWLP, and more recently the paradigm shift to Panel fan out Packaging. The work reports on lithography solutions for CD control over topography and high aspect ratio imaging of 2μm line/space RDL. In addition, the introduction of new inspection capabilities for defects and metrology is reported for both wafers and panels. The increase in lithography productivity and cost reduction provided by FOPLP is also discussed with production examples.

Enhancements to Picosecond Acoustic Metrology for application in FO-WLP Process

2018 ◽  
Vol 2018 (1) ◽  
pp. 000212-000216
Author(s):  
M. Mehendale ◽  
R. Mair ◽  
J. Chen ◽  
J. Tan ◽  
J. Dai ◽  
...  
Keyword(s):  
High Resolution ◽  
Cross Section ◽  
Large Scale ◽  
Low Cost ◽  
Critical Role ◽  
Under Bump Metallization ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Advanced Packaging ◽  
Line Space

Abstract Fan out wafer level packaging (FO-WLP) is one of the fastest growing advanced packaging segments due to its versatility for a wide variety of applications. It's compatibility with large scale, low cost, ultra-thin and high-density packages has made it very attractive. Cu redistribution layer and multiple metal under bump metallization stack play critical role in the FO-WLP process especially with shrinking line/space size and increasing density. We previously discussed the adaptation of PULSE™ technology, with the integration of a visible reflectometer and high resolution camera as a comprehensive in-line metrology tool for the advanced packaging applications. In this paper, we present results from some recent work on enhancements to the configuration for measurements of very thick, rough RDL films. The modifications provided significant improvement (9×) to throughput while maintaining gage capable repeatability. Cross-section SEM measurements on 1μm RDL structures were used to validate the extendibility of the technique.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Current status and future prospects of panel level packaging

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000707-000750
Author(s):  
Santosh Kumar ◽  
Amandine Pizzagalli ◽  
Dave Towne ◽  
Thibault Buisson ◽  
Andrej Ivankovic ◽  
...  
Keyword(s):  
Semiconductor Industry ◽  
High Volume ◽  
Current Status ◽  
Flat Panel Display ◽  
Future Prospects ◽  
Wafer Level ◽  
Commercial Development ◽  
Economy Of Scale ◽  
Wafer Level Packaging ◽  
Advanced Packaging

Demand of lower cost with higher performances has driven the semiconductor industry to develop innovative solutions. One of the new approaches to reduce the overall cost is to switch from wafer to larger size panel format. The panel infrastructure has gained considerable interest from the semiconductor industry and is certainly a promising market due to its cost advantages and economy of scale benefits. Panel level manufacturing has the potential to leverage the knowledge and infrastructure of wafer level packaging as well as PCB / flat panel display / photovoltaic industries. We have identified six key packaging platforms which can be processed on larger surface (rectangular/square) such as FOWLP panel, organic interposer, glass panel interposer, hybrid interposer, embedded die as well as coreless substrate. Over the past years, it's become clear that some panel packages choices will be more suitable than others for successful commercial development. The equipment infrastructure within the advanced packaging supply chain today is mainly based on processing 300mm round wafers. However, to process larger surface, new equipment and optimized materials are required. The key question raised is when the panel industry will take off and how will it evolve? Are the supply chains ready to move to the panel scale manufacturing? What are the challenges / issues involved for the panel adoption to high volume manufacturing? This paper will try to answer these questions and discuss about the current status and future prospects of panel level packaging.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Innovative 3D Structures Utilizing Wafer Level Fan-Out (WLFO) Technology

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001486-001519
Author(s):  
Curtis Zwenger ◽  
JinYoung Khim ◽  
YoonJoo Khim ◽  
SeWoong Cha ◽  
SeungJae Lee ◽  
...  
Keyword(s):  
Low Cost ◽  
Ease Of Use ◽  
Wafer Level ◽  
3D Structures ◽  
Wafer Level Packaging ◽  
Functional Convergence ◽  
3D Packaging ◽  
Improved Design ◽  
On Chip ◽  
Mobile Handset

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need, such as Thru Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP). In particular, the emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Wafer Level Fan-Out is a package technology designed to provide increased I/O density within a reduced footprint and profile for low density single & multi-die applications at a lower cost. The improved design capability of WLFO is due, in part, to the fine feature capabilities associated with wafer level packaging. This can allow much more aggressive design rules to be applied compared to competing laminate-based technologies. In addition, the unique characteristics of WLFO enable innovative 3D structures to be created that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of WLFO and its extension into unique 3D structures. In addition, the advantages of these WLFO designs will be reviewed in comparison to current competing packaging technologies. Process & material characterization, design simulation, and reliability data will be presented to show how WLFO is poised to provide robust, reliable, and low cost 3D packaging solutions for advanced mobile and networking products.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Improved compensation for a reduction stepper to meet the challenges for advanced packaging applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000814-000819 ◽  
Author(s):  
James E Webb ◽  
Steven Gardner ◽  
Elvino DaSilveira
Keyword(s):  
Leading Edge ◽  
Image Features ◽  
Wafer Level ◽  
Projection Lens ◽  
Wafer Level Packaging ◽  
Alignment System ◽  
Wide Range ◽  
Advanced Packaging ◽  
Volume Production ◽  
Mix And Match

Advanced packaging manufacturers require steppers that will provide solutions for the challenges encountered with new advances in wafer-level packaging technologies such as TSV, eWLB, silicon and glass interposers being utilized in leading edge mobile devices. Step and repeat photolithography systems capable of finer imaging with tighter overlay are being introduced to meet the challenging manufacturing requirements associated with the mix and match needed for volume production on larger wafers. A 2X reduction stepper with unique features incorporated that extend the range of compensation is necessary to achieve the tighter specifications needed for many advanced packaging applications printed on 300 to 450mm wafers. A high throughput projection optical system is used to expose circuit patterns from a reticle mask onto a substrate to image features with the optimal fidelity required for advanced packaging technologies. The camera incorporates 350–450nm light from a mercury arc lamp that is transmitted through the mask containing circuit patterns. The imaging field prints a large 52mm × 66mm area in a single exposure. These features enable a system to process wafers in fewer shots which result in higher throughput using lower power. Substrates are positioned with a precise X, Y, Θ stage by locating marks using an off-axis, bright field alignment system with fully trainable mark feature capability. The approach results in precisely placed features within a layer and from layer to layer without directly referencing the reticle. The integrated metrology and precision positioning subsystem technologies are combined with a low distortion projection lens and a wide range of adjustments, allowing the stepper to be integrated into a production line in a mix and match setup with other lithography systems. This equipment can be used to image critical layers on substrates while ensuring grid registration and alignment with other lithography systems that are also printing images in the same process line. Several important global and intra-field image placement relationships for devices requiring multiple layer patterning have been combined in the stepper matching correction software. Further adjustment to the tool can be made to improve overlay when incorporated with fab-wide yield management software for automated, real-time process control. The types of adjustments needed and techniques that can be applied to compensate for image placement errors over large areas are discussed.

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

scholarly journals Design and Fabrication of Wafer-Level Microlens Array with Moth-Eye Antireflective Nanostructures

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 747 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Bo Yang ◽  
Wei Zhang ◽  
Xiaoxiao Wei ◽  
...  
Keyword(s):  
Nanoimprint Lithography ◽  
Production Efficiency ◽  
Low Cost ◽  
Microlens Array ◽  
Wafer Level ◽  
Lens Array ◽  
Wafer Level Packaging ◽  
High Production ◽  
Aspherical Lenses ◽  
Profile Accuracy

Wafer-level packaging (WLP) based camera module production has attracted widespread industrial interest because it offers high production efficiency and compact modules. However, suppressing the surface Fresnel reflection losses is challenging for wafer-level microlens arrays. Traditional dielectric antireflection (AR) coatings can cause wafer warpage and coating fractures during wafer lens coating and reflow. In this paper, we present the fabrication of a multiscale functional structure-based wafer-level lens array incorporating moth-eye nanostructures for AR effects, hundred-micrometer-level aspherical lenses for camera imaging, and a wafer-level substrate for wafer assembly. The proposed fabrication process includes manufacturing a wafer lens array metal mold using ultraprecise machining, chemically generating a nanopore array layer, and replicating the multiscale wafer lens array using ultraviolet nanoimprint lithography. A 50-mm-diameter wafer lens array is fabricated containing 437 accurate aspherical microlenses with diameters of 1.0 mm; each lens surface possesses nanostructures with an average period of ~120 nm. The microlens quality is sufficient for imaging in terms of profile accuracy and roughness. Compared to lenses without AR nanostructures, the transmittance of the fabricated multiscale lens is increased by ~3% under wavelengths of 400–750 nm. This research provides a foundation for the high-throughput and low-cost industrial application of wafer-level arrays with AR nanostructures.

Low-cost wafer level packaging process

2000 ◽  
Author(s):  
Rahul Kapoor ◽  
Swee Y. Khim ◽  
Goh H. Hwa
Keyword(s):  
Low Cost ◽  
Wafer Level ◽  
Packaging Process ◽  
Wafer Level Packaging
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