3D Integration of System-in-Package (SiP) Using Organic Interposer: Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (1) ◽  
pp. 000531-000537 ◽  
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and embedded passives provides a high wireability package with excellent communication from top to bottom. In the present study, we also report a novel 3D “Package-Interposer-Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions incorporating various SiP configurations.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000618-000634 ◽  
Author(s):  
Rabindra Das ◽  
Frank D. Egitto ◽  
Steven G. Rosser ◽  
Erich Kopp ◽  
Barry Bonitz
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Integrated Approach ◽  
Solder Paste ◽  
Printed Wiring Board ◽  
3D Integration ◽  
Passive Components ◽  
Chip Technology ◽  
Small Pitch ◽  
Electrically Conductive Adhesive

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

Package-Interposer-Package (PIP): A Breakthrough Package-on-Package (PoP) Technology for 3D-Integration

2012 ◽  
Vol 2012 (1) ◽  
pp. 000561-000567
Author(s):  
Rabindra N. Das ◽  
Frank D. Egitto ◽  
Barry Bonitz ◽  
Erich Kopp ◽  
Mark D. Poliks ◽  
...  
Keyword(s):  
System Integration ◽  
Integrated Approach ◽  
Power Delivery ◽  
Solder Paste ◽  
3D Integration ◽  
Electrically Conductive ◽  
Reflow Temperature ◽  
Electrically Conductive Adhesive ◽  
The Stability ◽  
Electrical Connections

Package on Package (PoP) stacking has become an attractive method for 3D integration to meet the demands of higher functionality in ever smaller packages, especially when coupled with the use of stacked die. To accomplish this, new packaging designs need to be able to integrate more dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. A new 3D “Package Interposer Package” (PIP) solution is suitable for combining multiple memory, ASICs, stacked die, stacked packaged die, etc., into a single package. This approach also favors system integration with high density power delivery by appropriate interposer design and thermal management. Traditional Package on Package (PoP) approaches use direct solder connections between the substrates and are limited to use of single (or minimum) die on the bottom substrate, to reduce warpage and improve stability. For PIP, the stability imparted by the interposer reduces warpage, allowing assemblers of the PIP to select the top and bottom components (substrates, die, stacked die, modules) from various suppliers. This mitigates the problem of variation in warpage trends from room temperature to reflow temperature for different substrates/modules when combined with other packages. PIP facilitates more space-efficient designs, and can accommodate any stacked die height without compromising warpage and stability. PIP can accommodate modules with stacked die on organic, ceramic, or silicon board substrates, where each can be detached and replaced without affecting the rest of the package. Thus, PIP will be economical for high-end electronics, since a damaged, non-factional part of the package can be selectively removed and replaced. A variety of interposer structures were used to fabricate Package Interposer Package (PIP) modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP constructions on various stacked die or stacked packaged die configurations.

Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview

2019 ◽  
Vol 3 (1) ◽  
pp. 69-83 ◽  
Author(s):  
Madhav Datta
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Void Formation ◽  
High Volume ◽  
Lead Free ◽  
Manufacturing Processes ◽  
Solder Paste ◽  
Chip Technology

Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so that the entire surface of the chip can be covered with bumps for the highest possible input/output (I/O) counts. The present article reviews the manufacturing processes for the fabrication of flip-chip bumps for chip–package interconnection. Various solder bumping technologies used in high-volume production include evaporation, solder paste screening and electroplating. Evaporation process produces highly reliable bumps, but it is extremely expensive and is limited to lead or lead-rich solders. Solder paste screening is cost-effective, but issues related to excessive void formation limits the process to low-end products. On the other hand, electrochemical fabrication of flip-chip bumps is an extremely selective and efficient process, which is extendible to finer pitch, larger wafers and a variety of solder compositions, including lead-free alloys. Electrochemically fabricated copper pillar bumps offer fine pitch capabilities with excellent electromigration performance. Due to these virtues, the copper pillar bumping technology is emerging as a lead-free bumping technology option for high-performance electronic packaging.

Z-Interconnect Technology - A Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packaging

2014 ◽  
Vol 2014 (1) ◽  
pp. 000141-000147 ◽  
Author(s):  
John M. Lauffer ◽  
Kevin Knadle
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Performance Enhancement ◽  
High Density ◽  
Consumer Electronics ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Electrically Conductive Adhesive ◽  
Plated Through Hole ◽  
Interconnect Technology

Common themes across all segments of electronic packaging today are density and performance. High density interconnect (HDI) technology is one of the most commonly utilized methods for electronic package density improvement, while many different areas have been investigated for performance improvement, from low loss dielectric and conductor materials, to via design and via stub reduction. Electrical performance and density requirements are sometimes complementary, but often times, conflicting with one another. This paper will describe the design, materials, fabrication, and reliability of a new Z-Interconnect technology that addresses both high density and high performance demands simultaneously. Z-Interconnect technology uses an electrically conductive adhesive to electrically interconnect several cores (Full Z) or sub-composites (Sub Z) in a single lamination process. Z-Interconnect technology will be compared and contrasted to other commonly used solutions to the performance and density challenges. HDI or sequential build-up technology is a pervasive solution to the density demands in semiconductor packaging and consumer electronics (e.g. Smart phones), but has not caught hold in HPC or A&D printed wiring board (PWB) applications. One solution for PWB electrical performance enhancement is plated through hole (PTH) stub reduction by “back drilling” the unwanted portion of the PTH. Pb-free reflow and Current Induced Thermal Cycling (CITC) test results of product coupons and specially designed test vehicles, having component pitches down to 0.4mm, will be presented. Z-Interconnect test vehicles have survived 6X Pb-free (260C) reflow cycles, followed by greater than 3000 cycles of 23C–150C CITC cycles. Test vehicle and product coupons also easily survive 10 or more 23C–260C CITC cycles.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Silicon-Embedded RF Micro-Inductors for Ultra-Compact RF Subsystems

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 000939-000957
Author(s):  
Florian Herrault ◽  
M. Yajima ◽  
M. Chen ◽  
C. McGuire ◽  
A. Margomenos
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Silicon Wafers ◽  
High Resistivity ◽  
3D Integration ◽  
Passive Components ◽  
Capacitance Density ◽  
Embedded Passives ◽  
Lift Off ◽  
Rf Inductors

Advances in 2.5D and 3D integration technologies are enabling ultra-compact multi-chip modules. In this abstract, we present the design, fabrication, and experimental characterization of RF inductors microfabricated inside deep silicon recesses. Because silicon is often used as a substrate of packaging material for 3D integration and microelectromechanical systems (MEMS), developing microfabrication technologies to embed passive components in the unused volume of the silicon package is a promising approach to realize ultra-compact RF subsystems. Inductors and capacitors are critical in dc-bias circuits for MMICs in order to suppress low-frequency oscillations. Because it is particularly important to have these passive components as close to the MMIC as possible with minimum interconnection parasitics, silicon-embedded passives are an attractive solution. Further, silicon-embedded passives can potentially reduce the overall volume of RF subsystems when compared to modules using discrete passives. Although inductors inside the volume of silicon wafers have previously been reported, they typically operated in the 1–200 MHz frequency range, mostly featuring inductors with wide (50–100 μm) conductors and wide (50–100 μm) interconductor gaps due to fabrication limitations. We first explored process limitations to fabricate structural and electrical features inside 75 to 100-μm-deep silicon cavities. The cavities were etched into the silicon using deep reactive ion etching. Inside these recesses, we demonstrated the fabrication of thin (0.2 μm) and thick (5 μm) gold patterns with 3 μm resolution using lift-off and electroplating processes, respectively. The lift-off process used an image reversal technique, and the plated gold conductors were fabricated through a 6.5-μm-thick photoresist mold. The feature sizes ranged from 3 to 50 μm. For photoresist exposure, an i-line Canon stepper was utilized, and configured specifically to focus at the bottom of the cavities, a key process requirement to achieve high-resolution features. These microfabrication results enabled the design of high-performance RF inductors, which will be discussed in the next section. In addition, we demonstrated the fabrication of 30-μm-deep 3-μm-diameter silicon-etched features inside these cavities, a stepping stone towards achieving high-capacitance-density integrated trench capacitors embedded inside silicon cavities. The silicon-embedded RF inductors were microfabricated on 500-μm-thick high-resistivity (ρ > 20,000 Ω.cm) silicon wafers. First, 75-μm-deep cavities were etched using DRIE. Various two-port coplanar waveguide (CPW) inductor designs were microfabricated. The inductor microfabrication relied on sputtered titanium/gold seed layers, thick AZ4620 photoresist molds, and three 5-μm-thick electroplated gold layers stacked on top of each other to define the inductor conductor and connections. By using a combination of three electroplated layers, high-power-handling low-loss inductors were fabricated. Measurements were performed on a RF probe station, with on-wafer calibration structures. The losses associated with the CPW launchers were de-embedded prior to inductor measurements, and inductor quality factor greater than 40 was measured on various inductors with inductance of approximately 1 nH, and self-resonant frequency at 30 GHz. These results were in agreement with models performed using SONNET simulation package, and are comparable with than that of inductors fabricated on planar silicon wafers.

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Interface Adhesion and Reliability of Microsystem Packaging

2003 ◽  
Vol 782 ◽  
Author(s):  
Marvin I. Francis ◽  
Kellen Wadach ◽  
Satyajit Walwadkar ◽  
Junghyun Cho
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Dissimilar Materials ◽  
Strain Energy Release ◽  
Interface Adhesion ◽  
Curing Conditions ◽  
Chip Technology ◽  
Solder Balls ◽  
Cte Mismatch

ABSTRACTFlip-chip technology is becoming one of the most promising packaging techniques for high performance packages. Solder balls are used as the connection technique in the flip-chip method and the connections are reinforced by filling in the spacing between the chip and substrate with underfill. The function of the underfill is to reduce the stresses in the solder joints caused by a coefficient of thermal expansion (CTE) mismatch. The presence of polymeric underfill material will, however, make the flip-chip packaging system susceptible to interfacial failure. Thus, the purpose of this study is to examine the interfacial delamination between the dissimilar materials in order to increase the reliability of the flip-chip interconnection method, and to understand the effect of underfill curing conditions on the interface adhesion. In particular, we use a linear elastic fracture mechanics (LEFM) approach to assess interfacial toughness. For this purpose, four-point bending testing is performed to determine a critical strain energy release rate, Gc. In addition, nano-indentation testing equipped with atomic force microscope (AFM) is employed to determine structure and properties of the underfill layer.

Manufacturing Substrates with Embedded Passives

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002011-002050
Author(s):  
Rabindra N. Das ◽  
Konstantinos I. Papathomas ◽  
John M. Lauffer ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Electrical Characterization ◽  
Printed Wiring Board ◽  
Digital Products ◽  
Capacitance Density ◽  
Embedded Passives ◽  
Wiring Board ◽  
Electronic Assemblies

Passives account for a very large part of today's electronic assemblies. This is particularly true for digital products such as cellular phones, camcorders, computers and several critical defense devices. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on organic multilayered substrates. A variety of thin film capacitor and resistors were utilized to manufacture high-performance embedded passives. The electrical properties of capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide temperature range. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. In both cases, capacitance values are defined by the feature size, thickness and dielectric constant of the polymer-ceramic compositions. Nanocomposite can be directly deposited either by liquid coating or screen printing. Alternatively, nanocomposite thin films can be laminated and capacitor laminate can be used as the base substrate for subsequent build-up processing. For example, Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. The capacitor fabrication is based on a sequential build-up technology employing a first patternable electrode. After patterning of the electrode, RC3 nanocomposite can be laminated within PCB. Embedded passive cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. Reliability of the capacitors was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1000 cycles DTC (Deep Thermal Cycle).

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