Simulation and Comparison of Voltage and Current Characteristics of Novel Finfet by Varying its Oxide Thickness with Single Gate Mosfet for Improved Conductivity

Aim: The current and voltage characteristics of FinFET and single gate MOSFET are simulated by varying their oxide thickness ranging from 2 nm to 20 nm. Materials and Methods: The electrical conductance of FINFET (n= 320) was compared with MOSFET (n=320) by varying oxide thickness ranging from 2 nm to 20 nm in the NANO HUB tool simulation environment. Results: FINFET has significantly higher conductance (2.66*10-4 mho P<0.05) than single gate MOSFET (1.64*10-4 mho). The optimal thickness for maximum conductivity was 2nm for FINFET, and 2 nm for MOSFET. Conclusion: Within the limits of this study, FINFET with oxide thickness of 2 nm offers the best conductivity.

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Simulation of Carbon Nanotube based Field Effect Transistor by Varying Gate Oxide Thickness to Explore its Electrical Property and Compare it with Standard Mosfet

Revista Gestão Inovação e Tecnologias ◽

10.47059/revistageintec.v11i2.1780 ◽

2021 ◽

Vol 11 (2) ◽

pp. 1549-1566

Author(s):

Morupuri Satish Kumar Reddy

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Electrical Conductance ◽

Gate Oxide ◽

Oxide Thickness ◽

Simulation Environment ◽

Optimal Thickness ◽

Gate Oxide Thickness ◽

Maximum Conductivity ◽

Effect Transistor

Aim: The current and voltage characteristics of CNTFET and MOSFET are simulated by varying their gate oxide thickness ranging from 3.5nm to 11.5nm. Materials and Methods: The electrical conductance of CNTFET (n = 320) was compared with MOSFET (n = 320) by varying gate oxide thickness ranging from 3.5nm to 11.5nm in the NanoHUB© tool simulation environment. Results: CNTFET has significantly higher conductance (12.52 mho) than MOSFET (12.07 mho). The optimal thickness for maximum conductivity was 4nm for CNTFET and 3.5 nm for MOSFET. Conclusion: Within the limits of this study, CNTFET with the gate oxide thickness of 4 nm offers the best conductivity.

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Simulation and Comparison of Current Voltage Characteristics of Si and Ge based Bio Field Effect Transistor by Varying Oxide Thickness to Get Better Sensitivity

Revista Gestão Inovação e Tecnologias ◽

10.47059/revistageintec.v11i2.1737 ◽

2021 ◽

Vol 11 (2) ◽

pp. 1066-1083

Author(s):

S. Layasree

Keyword(s):

Field Effect Transistor ◽

Electrical Conductance ◽

Oxide Thickness ◽

Simulation Environment ◽

Current Voltage ◽

Gate Oxide Thickness ◽

Maximum Conductivity ◽

Current Voltage Characteristics ◽

Effect Transistor ◽

Silicon Based

Aim: The current voltage characteristics of Silicon based BIOFET and Germanium based BIOFET are simulated by varying their oxide thickness ranging from 1nm to 100nm. Materials and Methods: The electrical conductance of Silicon based BIOFET (n=320) was compared with Germanium based BIOFET (n=320) by varying oxide thickness ranging from 1nm to 100nm in the NanoHub© tool simulation environment. Results: Germanium based BIOFET has significantly higher conductance than Silicon based BIOFET. The optimal gate oxide thickness for maximum conductivity was 1nm for Silicon based BIOFET and 35nm for Germanium based BIOFET. Conclusion: Within the limits of the study, Germanium based BIOFET with oxide thickness of 35nm offers the best conductivity.

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Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

Active and Passive Electronic Components ◽

10.1155/2017/5947819 ◽

2017 ◽

Vol 2017 ◽

pp. 1-8 ◽

Cited By ~ 6

Author(s):

Satyam Shukla ◽

Sandeep Singh Gill ◽

Navneet Kaur ◽

H. S. Jatana ◽

Varun Nehru

Keyword(s):

Process Parameters ◽

Simulation Analysis ◽

Oxide Thickness ◽

Channel Length ◽

Deep Submicron ◽

Device Structure ◽

Short Channel ◽

20 Nm ◽

The Impact ◽

Fin Shape

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

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The Observation of Electrical Hysteric Behavior in Synthesized V2O5Nanoplates by Recrystallization

Journal of Nanomaterials ◽

10.1155/2013/807895 ◽

2013 ◽

Vol 2013 ◽

pp. 1-7 ◽

Cited By ~ 3

Author(s):

Chang-Hee Kim ◽

Yong Ju Yun ◽

Byung Hoon Kim ◽

Won G. Hong ◽

Yark Yeon Kim ◽

...

Keyword(s):

Electron Microscopy ◽

Annealing Temperature ◽

Electrical Conductance ◽

Anomalous Behavior ◽

Physical Analysis ◽

Scanning Calorimetry ◽

Transmission Electron ◽

Analysis Technique ◽

Voltage Dependent ◽

Current Characteristics

The anomalous electrical conductance for the V2O5foam synthesized via a foaming process was measured. In the annealing process, the synthesized V2O5foam is recrystallized with the increase of annealing temperature. The recrystallization procedure was characterized by using physical analysis tools such as thermogravimetric analysis (TGA), differential scanning calorimetry (DSC), scanning electron microscopy (SEM), high-resolution transmission electron microscopy (HRTEM), and X-ray diffractometer. In the electrical analysis technique of current-voltage characteristics as a function of annealing temperature, an anomalous hysteric behavior appears at the annealing temperature of 400°C. We conclude that the recrystallization of V2O5nanoplates results in the anomalous behavior in voltage-dependent current characteristics.

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Sensitive Capacitive-type Hydrogen Sensor Based on Ni Thin Film in Different Hydrogen Concentrations

Current Nanoscience ◽

10.2174/1573413713666171002124909 ◽

2018 ◽

Vol 14 (2) ◽

pp. 136-142 ◽

Cited By ~ 7

Author(s):

Ghobad Behzadi Pour ◽

Leila Fekri Aval ◽

Shahnaz Eslami

Keyword(s):

Thin Film ◽

Oxide Film ◽

Film Thickness ◽

Hydrogen Concentration ◽

Recovery Time ◽

Oxide Thickness ◽

Fast Response ◽

Oxide Film Thickness ◽

Mos Sensor ◽

20 Nm

Background: Hydrogen sensors are micro/nano-structure that are used to locate hydrogen leaks. They are considered to have fast response/recovery time and long lifetime as compared to conventional gas sensors. In this paper, fabrication of sensitive capacitive-type hydrogen gas sensor based on Ni thin film has been investigated. The C-V curves of the sensor in different hydrogen concentrations have been reported. Method: Dry oxidation was done in thermal chemical vapor deposition furnace (TCVD). For oxidation time of 5 min, the oxide thickness was 15 nm and for oxidation time 10 min, it was 20 nm. The Ni thin film as a catalytic metal was deposited on the oxide film using electron gun deposition. Two MOS sensors were compared with different oxide film thickness and different hydrogen concentrations. Results: The highest response of the two MOS sensors with 15 nm and 20 nm oxide film thickness in 4% hydrogen concentration was 87.5% and 65.4% respectively. The fast response times for MOS sensors with 15 nm and 20 nm oxide film thickness in 4% hydrogen concentration was 8 s and 21 s, respectively. Conclusion: By increasing the hydrogen concentration from 1% to 4%, the response time for MOS sensor (20nm oxide thickness), was decreased from 28s to 21s. The recovery time was inversely increased from 237s to 360s. The experimental results showed that the MOS sensor based on Ni thin film had a quick response and a high sensitivity.

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Hydrothermal Synthesis and Properties of Ce1−xMxO2-δ(M = La, Bi, Sm, Pr, Tb) Solid Solutions

MRS Proceedings ◽

10.1557/proc-548-511 ◽

1998 ◽

Vol 548 ◽

Cited By ~ 1

Author(s):

M. Greenblatt ◽

P. Shuk ◽

W. Huang ◽

S. Dikmen ◽

M. Croft

Keyword(s):

Solid Solutions ◽

Ultrafine Particles ◽

Electronic Conductivity ◽

Solubility Limit ◽

Hydrothermal Conditions ◽

Oxide Systems ◽

Oxide Ion Conductivity ◽

Maximum Conductivity ◽

Crystallite Dimension ◽

20 Nm

ABSTRACTA systematic study of hydrothermally prepared Ce1−x,MxO2−δ, (M= Sm, Bi, Pr, Tb; x= 0-0.30) solid solutions, promising materials for application in solid oxide fuel cells and oxygen membranes is presented. Ultrafine particles of uniform crystallite dimension, ∼ 20 nm can be formed in 30 min. under hydrothermal conditions (260°C, 10 MPa). The small particle size (20-50 nm) of the hydrothermally prepared materials allows sintering of the samples into highly dense ceramics at 900-1350°C, significantly lower temperatures than 1600-1650°C required for samples prepared by solid state techniques. The solubility limit of Bi2O3, in CeO2, was determined to be around 20 mol. %. The maximum conductivity, σ600°C ∼ 4.4 × 10−3 S/cm with Ea = 1.01 eV, and σ600°C = 5.7 × 10−3 S/cm with Ea ≈ 0.9 eV was found at x= 0.20 and x= 0.17 for Bi and Sm, respectively. In the Ce-Pr/Tb oxide systems, in addition to the high oxide ion conductivity, electronic conductivity occurs through the hopping of small polarons by a thermally activated mechanism (electron hopping from the Pr3+/Tb3+ to a neighboring Pr4+/Tb4+ ion).

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Silicon oxidation and Si–SiO2 interface of thin oxides

Journal of Materials Research ◽

10.1557/jmr.1987.0216 ◽

1987 ◽

Vol 2 (2) ◽

pp. 216-221 ◽

Cited By ~ 36

Author(s):

N. M. Ravindra ◽

J. Narayan ◽

Dariush Fathy ◽

J. K. Srivastava ◽

E. A. Irene

Keyword(s):

Refractive Index ◽

High Resolution ◽

Silicon Oxide ◽

Dielectric Breakdown ◽

Oxide Thickness ◽

Physical Parameters ◽

Growth Data ◽

Linear Behavior ◽

Transmission Electron ◽

20 Nm

High-resolution transmission electron microscopy (HRTEM) and ellipsometry techniques have been employed to measure thicknesses of silicon oxide, grown at 800°C in dry oxygen, in the thickness range of 2–20 nm. While the oxide growth data measured from TEM obey a nearly linear behavior, those obtained from ellipsometry are seen to vary nonlinearly. The interface structure as function of the increasing oxide thickness was studied using HRTEM. At these oxidation temperatures, the earlier reported variations of roughness at the interface on the oxide thickness for oxides grown at 900°C are not seen. Attempts aimed at correlating the high-resolution transmission electron micrographs with some physical parameters like the refractive index and the dielectric breakdown lead to considerations of the importance of the effect of protrusions of silicon atoms of 1 mm size into SiO2 layers on the interface properties. These findings lead to explanations of some key features concerning the refractive index and density of thin SiO2.

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Electron Probe Microanalysis Through Coated Oxidized Surfaces

Microscopy and Microanalysis ◽

10.1017/s1431927619014715 ◽

2019 ◽

Vol 25 (05) ◽

pp. 1112-1129 ◽

Cited By ~ 1

Author(s):

Mike B. Matthews ◽

Ben Buse ◽

Stuart L. Kearns

Keyword(s):

Electron Probe Microanalysis ◽

Electron Probe ◽

Low Voltage ◽

Layer Structure ◽

Oxide Thickness ◽

Linear Functions ◽

Voltage Electron ◽

Before And After ◽

20 Nm ◽

Good Agreement

AbstractLow voltage electron probe microanalysis (EPMA) of metals can be complicated by the presence of a surface oxide. If a conductive coating is applied, analysis becomes one of a three-layer structure. A method is presented which allows for the coating and oxide thicknesses and the substrate intensities to be determined. By restricting the range of coating and oxide thicknesses, tc and to respectively, x-ray intensities can be parameterized using a combination of linear functions of tc and to. tc can be determined from the coating element k-ratio independently of the oxide thickness. to can then be derived from the O k-ratio and tc. From tc and to the intensity components of the k-ratios from the oxide layer and substrate can each be derived. Modeled results are presented for an Ag on Bi2O3 on Bi system, with tc and to each ranging from 5 to 20 nm, for voltages of 5–20 kV. The method is tested against experimental measurements of Ag- or C-coated samples of polished Bi samples which have been allowed to naturally oxidize. Oxide thicknesses determined both before and after coating with Ag or C are consistent. Predicted Bi Mα k-ratios also show good agreement with EPMA-measured values.

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Comprehensive Optimization of Dual Threshold Independent-Gate FinFET and SRAM Cells

Active and Passive Electronic Components ◽

10.1155/2018/4512924 ◽

2018 ◽

Vol 2018 ◽

pp. 1-10 ◽

Cited By ~ 3

Author(s):

Haiyan Ni ◽

Jianping Hu ◽

Huishan Yang ◽

Haotian Zhu

Keyword(s):

Work Function ◽

Oxide Thickness ◽

Model Parameters ◽

Gate Electrode ◽

Noise Margin ◽

Comprehensive Method ◽

Current Characteristics ◽

Static Noise ◽

Independent Gate ◽

Tcad Simulations

Independent-Gate (IG) FinFET is a promising device in circuit applications due to its two separated gates, which can be used independently. In this paper, we proposed a comprehensive method to optimize the Dual Threshold (DT) IG FinFET devices by carrying out modulations for the gate electrode work function, oxide thickness, and silicon body thickness. Titanium nitride (TiNx) is used as the tunable work function gate electrode for good performances. The thicknesses of the gate oxide and silicon body are swept by TCAD simulations to obtain the appropriate values. The verification simulation of the optimized transistors shows that the DT IG FinFETs can realize merging parallel and series transistors, respectively, and the current characteristics of the transistors are improved significantly. By extracting the BSIM-IMG model parameters, we can simulate the circuits composed of the proposed DT IG FinFET by using HSPICE with BSIM-IMG model. As practical examples, we optimized two novel 7T SRAM cells using DT IG FinFETs. HSPICE simulation results indicate that the new SRAM cells obtain higher write margin and read static noise margin with lower leakage power consumption than the other implementations.

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