scholarly journals A curvature-corrected CMOS bandgap reference

2005 ◽  
Vol 1 ◽  
pp. 181-184
Author(s):  
O. Mitrea ◽  
C. Popa ◽  
A. M. Manolescu ◽  
M. Glesner
Keyword(s):  
Power Consumption ◽  
Cmos Technology ◽  
Measured Temperature ◽  
Bandgap Reference ◽  
Voltage Reference ◽  
Weak Inversion ◽  
Chip Area ◽  
Curvature Correction ◽  
Small Correction ◽  
Correction Technique

Abstract. This paper presents a CMOS bandgap reference that employs a curvature correction technique for compensating the nonlinear voltage temperature dependence of a diode connected BJT. The proposed circuit cancels the first and the second order terms in the VBE(T ) expansion by using the current of an autopolarizedWidlar source and a small correction current generated by a MOSFET biased in weak inversion. The voltage reference has been fabricated in a 0.35µm 3Metal/2Poly CMOS technology and the chip area is approximately 70µm × 110µm. The measured temperature coefficient is about 10.5 ppm/K over a temperature range of 10– 90°C while the power consumption is less than 1.4mW.

LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR

2009 ◽  
Vol 18 (03) ◽  
pp. 519-534 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Mos Transistor ◽  
Curvature Correction ◽  
Current Consumption ◽  
Correction Technique

Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

A High-Order Curvature-Compensated Bandgap Voltage Reference for Micro-Gyroscope

2012 ◽  
Vol 503 ◽  
pp. 12-17
Author(s):  
Qiang Li ◽  
Xiao Yun Tan ◽  
Guan Shi Wang
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Bandgap Reference ◽  
Voltage Reference ◽  
Temperature Dependent ◽  
Power Supply Voltage ◽  
Gyroscope System ◽  
Bandgap Voltage Reference ◽  
Reference Circuit

The reference is an important part of the micro-gyroscope system. The precision and stability of the reference directly affect the precision of the micro-gyroscope. Unlike the traditional bandgap reference circuit, a circuit using a temperature-dependent resistor ratio generated by a highly-resistive poly resistor and a diffusion resistor in CMOS technology is proposed in this paper. The complexity of the circuit is greatly reduced. Implemented with the standard 0.5μm CMOS technology and 9V power supply voltage, in the range of -40~120°C, the temperature coefficient of the proposed bandgap voltage reference can achieve to about 1.6 ppm/°C. The PSRR of the circuit is -107dB.

A 1.2 V 15–32 GHz low-power single-balanced gate mixer with a miniature rat-race hybrid

2012 ◽  
Vol 4 (4) ◽  
pp. 455-461
Author(s):  
Chung-Chun Chen ◽  
Chun-Hsien Lien ◽  
Hen-Wai Tsao ◽  
Huei Wang
Keyword(s):  
Power Consumption ◽  
Design Procedure ◽  
Local Oscillator ◽  
Cmos Technology ◽  
Conversion Gain ◽  
Conversion Loss ◽  
Power Budget ◽  
Digital Cmos ◽  
Chip Area ◽  
Dc Power

A 15–32 GHz miniature single-balanced gate mixer is proposed and analyzed. It achieves a smaller chip area with acceptable conversion gain and port-to-port isolation. In addition, the design procedure is described in detail. This mixer, fabricated in 90 nm digital CMOS technology, demonstrates a measured conversion loss of 1 dB and higher than 30 dB RF-to-LO port isolation from 17 to 32 GHz, at a local oscillator (LO) driver power of −4.3 dBm. The total dc power consumption is only 6 mW from a 1.2 V supply, including output buffer. The low dc power consumption and LO driver power reduce the power budget, and the proposed miniature rat-race hybrid facilitates integration in a receiver.

scholarly journals Design & Implementation of Low Power 3-bit Flash ADC in 0.18μm CMOS

2012 ◽  
pp. 89-93
Author(s):  
Pradeep Kumar ◽  
Amit Kolhe
Keyword(s):  
Power Consumption ◽  
Response Time ◽  
Low Power ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Chip Area ◽  
Flash Adc ◽  
Analog To Digital ◽  
Design And Implementation

This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The presimulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shoes the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2 .

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550086 ◽  
Author(s):  
Masoud Nazari ◽  
Leila Sharifi ◽  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Range ◽  
Logic Gates ◽  
Cmos Technology ◽  
Total Power ◽  
Current Steering ◽  
Domino Logic ◽  
Chip Area ◽  
Total Power Consumption

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

scholarly journals Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Fang Tang ◽  
Amine Bermak ◽  
Abbes Amira ◽  
Mohieddine Amor Benammar ◽  
Debiao He ◽  
...  
Keyword(s):  
Power Consumption ◽  
Error Correction ◽  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Sar Adc ◽  
Quantization Noise ◽  
Noise Performance ◽  
Chip Area ◽  
Full Resolution

Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

Thermally Reliable Ultra-Low-Power Voltage Reference to Regulator Converter

2020 ◽  
pp. 2150024
Author(s):  
George M. Joseph ◽  
Emmanouel George ◽  
Prathyush S. Pramod ◽  
Zameel Nizam ◽  
S. Krishnapriya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Current Efficiency ◽  
Power Supply ◽  
Cmos Technology ◽  
Surveillance Systems ◽  
Voltage Reference ◽  
Power Budget ◽  
Line Load ◽  
Ultra Low Power

A regulated power supply with ultra-low-power consumption, high current efficiency, line, load and thermal stability is an essential part of any high precision electronic system with stringent power budget such as biomedical sensors or military surveillance systems. In this paper, we propose an ultra-low-power, MOSFET only, voltage reference to regulator convertor, proficient to work below 1 V with reduced power consumption. The proposed idea incorporates the provision to integrate any voltage reference module to a comparator-based circuit so as to transform it to a voltage regulator having similar temperature coefficient (TC) and line regulation as that of the interfaced voltage reference. It is also able to produce a reliable output accounting to load fluctuations. The circuit is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology using Cadence Virtuoso simulation suit. The complete circuit was found to draw a quiescent current of 319.9 pA with a notable current efficiency of 99.99997% at 27∘C on driving a load of 1[Formula: see text]mA along with a Power Supply Rejection Ratio (PSRR) of [Formula: see text][Formula: see text]dB additional to that of the reference. The proposed circuit will occupy an area of 0.00064[Formula: see text]mm2 and offer a TC as low as 1.7077 ppm/∘C. The whole MOS approach facilitates a reduction in die area and process simplicity.

scholarly journals 16.8/15.2 ppm/°C 81 nW High PSRR Dual-Output Voltage Reference for Portable Biomedical Application

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 213 ◽  
Author(s):  
Hongwei Yue ◽  
Xiaofei Sun ◽  
Junxin Liu ◽  
Weilin Xu ◽  
Haiou Li ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Voltage ◽  
Biomedical Application ◽  
Cmos Process ◽  
Voltage Reference ◽  
Subthreshold Region ◽  
Chip Area ◽  
Power Supply Rejection Ratio ◽  
Current Mirrors ◽  
Reference Circuit

A dual-output voltage reference circuit with two reference voltages of 281 mV (Vref1) and 320.5 mV (Vref2) is presented in this paper. With a novel and precise circuit structure, the proposed circuit, operating in the subthreshold region, integrates two different output voltages into a circuit to form a dual-output voltage reference, and cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). The proposed circuit was designed in a standard 0.18-µm CMOS process and has a series of attractive features: low-temperature coefficient (TC), high-PSRR, low-Line sensitivity (LS), small-chip area and low-power consumption. Monte Carlo simulations for 2000 samples showed that the output voltages 281 mV and 320.5 mV had a variation coefficient of 1.73% and 1.44%, respectively. The minimum power consumption was 84.1 nW at 0.9 V supply, proving that the circuit is suitable for portable biomedical application. The active area of the proposed voltage reference was only 0.0086 mm2.

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