scholarly journals Graphene Growth and Characterization: Advances, Present Challenges and Prospects

2019 ◽  
Vol 8 (4) ◽  
pp. 37
Author(s):  
John U. Arikpo ◽  
Michael U. Onuu
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Frequency Multiplier ◽  
Optical Modulator ◽  
Super Capacitor ◽  
Graphene Growth ◽  
Dielectric Substrates ◽  
Substrate Engineering ◽  
Computational Analyses ◽  
The Impact

It is about a decade since graphene became a material for serious research by researchers in condensed matter of various nationalities making significant progress. This paper on graphene growth and characterization: advances, present challenges and prospects is therefore timely. Basic topics such as graphene and graphene technology, history and trend of graphene as well as graphene growth and synthesis have been discussed. Also presented are fundamental and mechanical properties, structural and morphological property characterization using different techniques. Graphene in biomedical and radio frequency applications, transparent electronics, integrated circuits, quantum dots, frequency multiplier, optical modulator and piezoelectricity and as a battery super capacitor are some applications and uses of graphene that have been considered. The lowering of the growth temperature of graphene has been found to be beneficial for the compartibility with other materials and processes and could also decrease the impact of cooling-induced wrinkling on the morphology of graphene; the growth on dielectric substrates; being able to resolve many problems associated with metallic growth substrates; better control of both the formation and the extension of additional layers on the graphene through substrate engineering that will result in approaches of graphene that is envisaged are some of the advances and future prospects. Also, the proposed tunable bandgap for graphene which is essential for microelectronics which contributes one of the present challenges is likely to be achieved in the very near future. Although theoretical and computational analyses have proved to have solved the zero bandgap problem of graphene, more convincing approaches that will solve the problem and give way for the fabrication of high performance graphene device are being awaited.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

scholarly journals Electrical and Mechanical Analysis of Different TSV Geometries

Metals ◽  
2020 ◽  
Vol 10 (4) ◽  
pp. 467
Author(s):  
Il Ho Jeong ◽  
Alireza Eslami Majd ◽  
Jae Pil Jung ◽  
Nduka Nnamdi Ekere
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Signal Transmission ◽  
Characteristic Impedance ◽  
Electrical Signal ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Silicon Chips ◽  
The Impact

Through-silicon via (TSV) is an important component for implementing 3-D packages and 3-D integrated circuits as the TSV technology allows stacked silicon chips to interconnect through direct contact to help facilitate high-speed signal processing. By facilitating the stacking of silicon chips, the TSV technology also helps to meet the increasing demand for high density and high performance miniaturized electronic products. Our review of the literature shows that very few studies have reported on the impact of TSV bump geometry on the electrical and mechanical characteristics of the TSV. This paper reports on the investigation of different TSV geometries with the focus on identifying the ideal shapes for improved electrical signal transmission as well as for improved mechanical reliability. The cylindrical, quadrangular (square), elliptical, and triangular shapes were investigated in our study and our results showed that the quadrangular shape had the best electrical performance due to good characteristic impedance. Our results also showed that the quadrangular and cylindrical shapes provided improved mechanical reliability as these two shapes lead to high Cu protrusion of TSV after the annealing process.

Overview of High Performance Packaging Materials

1990 ◽  
Vol 203 ◽  
Author(s):  
Barry C. Johnson
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Building Blocks ◽  
Electrical Performance ◽  
Electronic Systems ◽  
Circuit Performance ◽  
Signal Velocity ◽  
Semiconductor Chip ◽  
Thermal Cooling ◽  
The Impact

ABSTRACTHigh Performance Integrated Circuits form the basic building blocks of modern electronic systems that are designed to process ever larger numbers of electrical signals at greater signal velocity and fidelity. In such applications, each circuit must be packaged in order to provide it with necessary mechanical support, environmental protection, electrical interconnection and thermal cooling. The package, however, can also impose certain constraints on the chip. It can degrade electrical performance, add size and weight, introduce reliability problems and increase cost. Thus, packaging can be viewed as a complex balance between the provision of desired functions and the reduction of associated constraints.The ability to strike a proper balance has become increasingly difficult in recent years due to the relentless march of integrated circuits toward higher levels of complexity, size, speed, heat flux and customization. It is anticipated that the continuing evolution of high performance circuits and systems will soon be limited by the package designs and materials-of-construction, rather than by the devices on the semiconductor chip.The intent of this talk is to provide a brief overview of high performance packaging and the related materials issues. The approach is to (a) present the forecasted trends in relevant circuit performance characteristics, (b) discuss the impact of these characteristics on current chip and board level packaging methods, and (c) present new package and materials concepts that might furnish potential solutions to the developing circuit-package performance gap.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

Dietary Vitamin and Stability of Oral Anticoagulation: Proposal of a Diet with Constant Vitamin K1 Content

1997 ◽  
Vol 77 (03) ◽  
pp. 504-509 ◽  
Author(s):  
Sarah L Booth ◽  
Jacqueline M Charnley ◽  
James A Sadowski ◽  
Edward Saltzman ◽  
Edwin G Bovill ◽  
...  
Keyword(s):  
Dietary Intake ◽  
Vitamin K ◽  
High Performance ◽  
Case Reports ◽  
Food Composition ◽  
Dietary Guidelines ◽  
Dietary Vitamin ◽  
Vitamin K1 ◽  
The Stability ◽  
The Impact

SummaryCase reports cited in Medline or Biological Abstracts (1966-1996) were reviewed to evaluate the impact of vitamin K1 dietary intake on the stability of anticoagulant control in patients using coumarin derivatives. Reported nutrient-drug interactions cannot always be explained by the vitamin K1 content of the food items. However, metabolic data indicate that a consistent dietary intake of vitamin K is important to attain a daily equilibrium in vitamin K status. We report a diet that provides a stable intake of vitamin K1, equivalent to the current U.S. Recommended Dietary Allowance, using food composition data derived from high-performance liquid chromatography. Inconsistencies in the published literature indicate that prospective clinical studies should be undertaken to clarify the putative dietary vitamin K1-coumarin interaction. The dietary guidelines reported here may be used in such studies.

Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate

1998 ◽  
Author(s):  
Ching-Lang Chiang ◽  
Neeraj Khurana ◽  
Daniel T. Hurley ◽  
Ken Teasdale
Keyword(s):  
Integrated Circuits ◽  
Ccd Camera ◽  
Preparation Technique ◽  
Absorption Data ◽  
Ir Radiation ◽  
Heavily Doped ◽  
Emission Microscopy ◽  
Diffraction Patterns ◽  
Emission Detection ◽  
The Impact

Abstract Backside emission microscopy on heavily doped substrate materials was analyzed from the viewpoint of optical absorption by the substrate and sample preparation technique. Although it was widely believed that silicon is transparent to infrared (IR) radiation, we demonstrated by using published absorption data that silicon with doping levels above 5 x 1018cm-3 is virtually opaque, leaving only a narrow transmission window around the energy bandgap. Because the transmission depends exponentially on the thickness of die, thinning to below 100µm is shown to be required. Even an advanced IR sensor such as HgCdTe would find little light to detect without thinning the die. For imaging the circuit, an IR laser-based system produced poor images in which the diffraction patterns often ruined the contrast and obscured the image. Hence, a precise, controlled die thinning technique is required both for emission detection and backside imaging. A thinning and polishing technique was briefly described that was believed to be applicable to most ceramic packages. A software technique was employed to solve the image quality problem commonly encountered in backside imaging applications using traditional microscope light source and a scientific grade CCD camera. Finally, we showed the impact of die thickness on imaging circuits on a heavily doped n type substrate.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Alpha Tocopherol Loaded in Liposome: Preparation, Optimization, Characterization and Sperm Motility Protection

2020 ◽  
Vol 10 (3) ◽  
pp. 228-236 ◽  
Author(s):  
Lamia Taouzinet ◽  
Sofiane Fatmi ◽  
Allaeddine Khellouf ◽  
Mohamed Skiba ◽  
Mokrane Iguer-ouada
Keyword(s):  
Vitamin E ◽  
Sperm Motility ◽  
High Performance ◽  
Positive Impact ◽  
Alpha Tocopherol ◽  
Ethanol Injection ◽  
Liposome Preparation ◽  
Liposome Size ◽  
Optimum Solution ◽  
The Impact

Background: Alpha-tocopherol is a potent antioxidant involved in sperm protection particularly during cryopreservation. However, its poor solubility limits the optimal protection in aqueous solutions. Objective: The aim of this study was to enhance the solubility of α-tocopherol by the use of liposomes. Methods: The experimental approach consisted to load vitamin E in liposomes prepared by ethanol injection method and the optimization carried out by an experimental design. The optimum solution was characterized by high performance liquid chromatography and scanning electron microscope. Finely, the impact on sperm motility protection was studied by the freezing technic of bovine sperm. Results: The optimum solution was obtained when using 10.9 mg/ml of phospholipids, 1.7 mg/ml of cholesterol and 2 mg/ml of vitamin E. The liposome size was 99.86 nm, providing 78.47% of loaded efficiency. The results showed also a significant positive impact on sperm motility after hours of preservation. Conclusion: In conclusion, the current results showed the interest of liposome preparation as an alternative to enhance vitamin E solubility and to protect spermatozoa during cryopreservation.

Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation

2019 ◽  
Vol 12 (1) ◽  
pp. 30-39 ◽  
Author(s):  
Apangshu Das ◽  
Sambhu Nath Pradhan
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Logic Synthesis ◽  
Programmable Logic Arrays ◽  
Power Switching ◽  
Nsga Ii ◽  
Multi Level ◽  
Search Approach ◽  
Efficient Power ◽  
The Impact

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.

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