scholarly journals Electrical and Mechanical Analysis of Different TSV Geometries

Metals ◽  
2020 ◽  
Vol 10 (4) ◽  
pp. 467
Author(s):  
Il Ho Jeong ◽  
Alireza Eslami Majd ◽  
Jae Pil Jung ◽  
Nduka Nnamdi Ekere
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Signal Transmission ◽  
Characteristic Impedance ◽  
Electrical Signal ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Silicon Chips ◽  
The Impact

Through-silicon via (TSV) is an important component for implementing 3-D packages and 3-D integrated circuits as the TSV technology allows stacked silicon chips to interconnect through direct contact to help facilitate high-speed signal processing. By facilitating the stacking of silicon chips, the TSV technology also helps to meet the increasing demand for high density and high performance miniaturized electronic products. Our review of the literature shows that very few studies have reported on the impact of TSV bump geometry on the electrical and mechanical characteristics of the TSV. This paper reports on the investigation of different TSV geometries with the focus on identifying the ideal shapes for improved electrical signal transmission as well as for improved mechanical reliability. The cylindrical, quadrangular (square), elliptical, and triangular shapes were investigated in our study and our results showed that the quadrangular shape had the best electrical performance due to good characteristic impedance. Our results also showed that the quadrangular and cylindrical shapes provided improved mechanical reliability as these two shapes lead to high Cu protrusion of TSV after the annealing process.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Overview of High Performance Packaging Materials

1990 ◽  
Vol 203 ◽  
Author(s):  
Barry C. Johnson
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Building Blocks ◽  
Electrical Performance ◽  
Electronic Systems ◽  
Circuit Performance ◽  
Signal Velocity ◽  
Semiconductor Chip ◽  
Thermal Cooling ◽  
The Impact

ABSTRACTHigh Performance Integrated Circuits form the basic building blocks of modern electronic systems that are designed to process ever larger numbers of electrical signals at greater signal velocity and fidelity. In such applications, each circuit must be packaged in order to provide it with necessary mechanical support, environmental protection, electrical interconnection and thermal cooling. The package, however, can also impose certain constraints on the chip. It can degrade electrical performance, add size and weight, introduce reliability problems and increase cost. Thus, packaging can be viewed as a complex balance between the provision of desired functions and the reduction of associated constraints.The ability to strike a proper balance has become increasingly difficult in recent years due to the relentless march of integrated circuits toward higher levels of complexity, size, speed, heat flux and customization. It is anticipated that the continuing evolution of high performance circuits and systems will soon be limited by the package designs and materials-of-construction, rather than by the devices on the semiconductor chip.The intent of this talk is to provide a brief overview of high performance packaging and the related materials issues. The approach is to (a) present the forecasted trends in relevant circuit performance characteristics, (b) discuss the impact of these characteristics on current chip and board level packaging methods, and (c) present new package and materials concepts that might furnish potential solutions to the developing circuit-package performance gap.

scholarly journals Monitoring and characterization of vibration and shock conditions aboard high-performance marine craft

2018 ◽  
Vol 233 (4) ◽  
pp. 1068-1081
Author(s):  
Manudul Pahansen de Alwis ◽  
Karl Garme
Keyword(s):  
Real Time ◽  
High Speed ◽  
High Performance ◽  
Severity Index ◽  
Irregular Waves ◽  
Vibration Exposure ◽  
Data Set ◽  
Real Time Analysis ◽  
Impact Acceleration ◽  
The Impact

The stochastic environmental conditions together with craft design and operational characteristics make it difficult to predict the vibration environments aboard high-performance marine craft, particularly the risk of impact acceleration events and the shock component of the exposure often being associated with structural failure and human injuries. The different timescales and the magnitudes involved complicate the real-time analysis of vibration and shock conditions aboard these craft. The article introduces a new measure, severity index, indicating the risk of severe impact acceleration, and proposes a method for real-time feedback on the severity of impact exposure together with accumulated vibration exposure. The method analyzes the immediate 60 s of vibration exposure history and computes the severity of impact exposure as for the present state based on severity index. The severity index probes the characteristic of the present acceleration stochastic process, that is, the risk of an upcoming heavy impact, and serves as an alert to the crew. The accumulated vibration exposure, important for mapping and logging the crew exposure, is determined by the ISO 2631:1997 vibration dose value. The severity due to the impact and accumulated vibration exposure is communicated to the crew every second as a color-coded indicator: green, yellow and red, representing low, medium and high, based on defined impact and dose limits. The severity index and feedback method are developed and validated by a data set of 27 three-hour simulations of a planning craft in irregular waves and verified for its feasibility in real-world applications by full-scale acceleration data recorded aboard high-speed planing craft in operation.

scholarly journals Research on Blade-Casing Rub-Impact Mechanism by Experiment and Simulation in Aeroengines

2019 ◽  
Vol 2019 ◽  
pp. 1-15 ◽  
Author(s):  
Jie Hong ◽  
Tianrang Li ◽  
Zhichao Liang ◽  
Dayi Zhang ◽  
Yanhong Ma
Keyword(s):  
High Speed ◽  
High Performance ◽  
Element Model ◽  
Physical Parameters ◽  
Test Rig ◽  
Calculation Results ◽  
Rotor Support ◽  
Blade Tip ◽  
Set Up ◽  
The Impact

Aeroengines pursue high performance, and compressing blade-casing clearance has become one of the main ways to improve turbomachinery efficiency. Rub-impact faults occur frequently with clearance decreasing. A high-speed rotor-support-casing test rig was set up, and the mechanism tests of light and heavy rub-impact were carried out. A finite element model of the test rig was established, and the calculation results were in good agreement with the experimental results under both kinds of rub-impact conditions. Based on the actual blade-casing structure model, the effects of the major physical parameters including imbalance and material characteristics were investigated. During the rub-impact, the highest stress occurs at the blade tip first and then it is transmitted to the blade root. Deformation on the impact blade tip generates easily with decreased yield strength, and stress concentration at the blade tip occurs obviously with weaker stiffness. The agreement of the computation results with the experimental data indicates the method could be used to estimate rub-impact characteristics and is effective in design and analyses process.

Si-Ge heterojunction bipolar technology for high-speed integrated circuits

1996 ◽  
Vol 74 (S1) ◽  
pp. 159-166
Author(s):  
D. C. Ahlgren ◽  
S. J. Jeng ◽  
D. Nguyen-Ngoc ◽  
K. Stein ◽  
D. Sunderland ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Full Range ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Voltage Controlled Oscillators ◽  
Sige Hbt ◽  
Trade Offs ◽  
Scale Integration

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.

III-V HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED APPLICATIONS

1990 ◽  
Vol 01 (03n04) ◽  
pp. 245-301 ◽  
Author(s):  
M.F. CHANG ◽  
P.M. ASBECK
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
High Performance ◽  
Growth Parameters ◽  
Bipolar Transistors ◽  
System Requirements ◽  
Potential Impact ◽  
Computational Systems ◽  
Very High

Recent advances in communication, radar and computational systems demand very high performance electronic circuits. Heterojunction bipolar transistors (HBTs) have the potential of providing a more efficient solution to many key system requirements through intrinsic device advantages than competing technologies. This paper reviews the present status of GaAs and InP-based HBT technologies and their applications to digital, analog, microwave and multifunction circuits. It begins with a brief review of HBT device concepts and critical epitaxial growth parameters. Issues important for device modeling and fabrication technologies are discussed. The paper then highlights the performance and the potential impact of HBT devices and integrated circuits in various application areas. Key prospects for future HBT development are also addressed.

scholarly journals Graphene Growth and Characterization: Advances, Present Challenges and Prospects

2019 ◽  
Vol 8 (4) ◽  
pp. 37
Author(s):  
John U. Arikpo ◽  
Michael U. Onuu
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Frequency Multiplier ◽  
Optical Modulator ◽  
Super Capacitor ◽  
Graphene Growth ◽  
Dielectric Substrates ◽  
Substrate Engineering ◽  
Computational Analyses ◽  
The Impact

It is about a decade since graphene became a material for serious research by researchers in condensed matter of various nationalities making significant progress. This paper on graphene growth and characterization: advances, present challenges and prospects is therefore timely. Basic topics such as graphene and graphene technology, history and trend of graphene as well as graphene growth and synthesis have been discussed. Also presented are fundamental and mechanical properties, structural and morphological property characterization using different techniques. Graphene in biomedical and radio frequency applications, transparent electronics, integrated circuits, quantum dots, frequency multiplier, optical modulator and piezoelectricity and as a battery super capacitor are some applications and uses of graphene that have been considered. The lowering of the growth temperature of graphene has been found to be beneficial for the compartibility with other materials and processes and could also decrease the impact of cooling-induced wrinkling on the morphology of graphene; the growth on dielectric substrates; being able to resolve many problems associated with metallic growth substrates; better control of both the formation and the extension of additional layers on the graphene through substrate engineering that will result in approaches of graphene that is envisaged are some of the advances and future prospects. Also, the proposed tunable bandgap for graphene which is essential for microelectronics which contributes one of the present challenges is likely to be achieved in the very near future. Although theoretical and computational analyses have proved to have solved the zero bandgap problem of graphene, more convincing approaches that will solve the problem and give way for the fabrication of high performance graphene device are being awaited.

scholarly journals Silicon photonics for high data rate applications -INVITED

2020 ◽  
Vol 238 ◽  
pp. 01005
Author(s):  
David J. Thomson ◽  
Weiwei Zhang ◽  
Ke Li ◽  
Kapil Debnath ◽  
Shenghao Liu ◽  
...  
Keyword(s):  
Silicon Photonics ◽  
High Speed ◽  
High Performance ◽  
High Efficiency ◽  
Electrical Signal ◽  
Electronic Components ◽  
High Data ◽  
Electro Optic ◽  
Optical Domain ◽  
Linear Modulation

The high speed conversion of signals between the optical and electrical domains is crucial for many key applications of silicon photonics. Electro-optic modulators integrated with electronic drive amplifiers are typically used to convert an electrical signal to the optical domain. Design of these individual elements is important to achieve high performance, however a true optimisation requires careful co-design of the photonic and electronic components considering the properties of each other. Here we present our recent results in this area together with a MOSCAP type modulator with the potential for high speed, high efficiency and highly linear modulation.

Implant-induced strain-relaxation in SiGe/Si layers

1993 ◽  
Vol 51 ◽  
pp. 1112-1113
Author(s):  
N. David Theodore ◽  
Gordon Tam
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
High Speed ◽  
High Performance ◽  
Strain Relaxation ◽  
Base Material ◽  
Sige Layer ◽  
Bipolar Transistors ◽  
Leakage Currents ◽  
Extrinsic Base

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. SiGe is typically used as an epitaxial base material in HBTs. To obtain extremely high-performance bipolar-transistors it is necessary to reduce the extrinsic base-resistance. This can be done by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however with the use of implantation is that blanket implants have been found to enhance strain-relaxation of SiGe/Si. Strain relaxation will cause the bandgap-difference between Si and SiGe to decrease; this difference is maximum for a strained SiGe layer. The electrical benefits of using SiGe/Si arise largely from the presence of a significant bandgap-difference across the SiGe/Si interface. Strain relaxation reduces this benefit. Furthermore, once misfit or threading dislocations result (during strain-relaxation), the defects can give rise to recombination-generation in depletion regions of the device; high electrical leakage currents result.

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

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