scholarly journals Cost-effective and High-performance FBAR Duplexer Module with Wafer Level Packaging

2012 ◽  
Vol 16 (5) ◽  
pp. 1029-1034
Author(s):  
Hyun-Cheol Bae ◽  
Sung-Chan Kim
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Wafer Level ◽  
Wafer Level Packaging

Epitaxial and Non-Epitaxial Heterogeneous Integration Technologies at NGST

2008 ◽  
Vol 1068 ◽  
Author(s):  
Augusto Gutierrez-Aitken ◽  
Patty Chang-Chien ◽  
Bert Oyama ◽  
Kelly Tornquist ◽  
Khanh Thai ◽  
...  
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
Heterogeneous Integration ◽  
Space Technology ◽  
Wafer Level ◽  
Selective Epitaxial Growth ◽  
Wafer Level Packaging ◽  
Design Flexibility ◽  
Systems Requirements ◽  
And Performance

ABSTRACTTo meet increasingly challenging and complex systems requirements, it is not enough to use one single semiconductor technology but to integrate several high performance technologies in an efficient and cost effective way. Heterogeneous integration (HI) approaches lead to a significant higher design flexibility and performance. In this paper we present some of the HI approaches that are being used and developed at Northrop Grumman Space Technology (NGST) that include selective epitaxial growth, metamorphic growth and wafer level packaging (WLP) technology. More recently we are developing a scaled and selective wafer packaging technique to integrate III-V semiconductors with silicon under the COSMOS DARPA program.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

2014 ◽  
Vol 2014 (1) ◽  
pp. 000599-000605 ◽  
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Cost Effective ◽  
Disruptive Innovation ◽  
Design Rule ◽  
Wind Condition ◽  
Silicon Etching ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

2015 ◽  
Vol 12 (3) ◽  
pp. 111-117
Author(s):  
Woon-Seong Kwon ◽  
Suresh Ramalingam ◽  
Xin Wu ◽  
Liam Madden ◽  
C. Y. Huang ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Integration ◽  
Cost Effective ◽  
Design Rule ◽  
Innovative Technology ◽  
Wind Condition ◽  
Wafer Level ◽  
Effective Manner ◽  
Interconnect Technology

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging

2013 ◽  
Author(s):  
Maaike M. V. Taklo ◽  
Astrid-Sofie Vardøy ◽  
Ingrid De Wolf ◽  
Veerle Simons ◽  
H. J. van de Wiel ◽  
...  
Keyword(s):  
Residual Stress ◽  
Integrated Circuit ◽  
High Performance ◽  
White Light Interferometry ◽  
Wafer Level ◽  
Noticeable Effect ◽  
Micro Raman Spectroscopy ◽  
Wafer Level Packaging ◽  
Mems Device ◽  
Specific Technology

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

Bed of Nails: Fine Pitch Wafer-level Packaging Interconnects for High Performance Nano Devices

2006 ◽  
Author(s):  
Vempati Srinivasa Rao ◽  
V. Kripesh ◽  
Seung Wook Yoon ◽  
D. Witarsa ◽  
A.A.O. Tay
Keyword(s):  
High Performance ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Fine Pitch

A 3‐dB Quadrature WLP Coupler for 60 GHz Applications

2012 ◽  
Vol 1427 ◽  
Author(s):  
Hamid Kiumarsi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
Kenichi Okada ◽  
Yusuke Uemichi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
High Performance ◽  
Low Cost ◽  
Phase Error ◽  
Superior Performance ◽  
60 Ghz ◽  
Wafer Level ◽  
Chip Area ◽  
Wafer Level Packaging ◽  
Coupled Lines

ABSTRACTA 60 GHz tandem coupler using offset broadside coupled lines is proposed in a WLP (Wafer Level Packaging) technology. The fabricated coupler has a core chip area of 750 μm × 385 μm (0.288 mm2). The measured results show an insertion loss of 0.44 dB, an amplitude imbalance of 0.03 dB and a phase difference of 87.6° at 60 GHz. Also the measurement shows an insertion loss of less than 0.67 dB, an amplitude imbalance of less than 0.31 dB, a phase error of less than 3.7°, an isolation of more than 29.7 dB and a return loss of more than 27.9 dB at the input ant coupled ports and more than 14.3 dB at the direct and isolated ports over the frequency band of 57-66 GHz, covering 60 GHz band both in Japan and US. To the best of our knowledge the proposed coupler achieves the lowest ever reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate. With its superior performance and lower cost compared to the CMOS counterparts, the proposed coupler is a suitable candidate for low-cost high-performance millimeter-wave systems.

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