Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

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Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽

10.1557/s0883769400034151 ◽

1997 ◽

Vol 22 (10) ◽

pp. 19-27 ◽

Cited By ~ 86

Author(s):

Wei William Lee ◽

Paul S. Ho

Keyword(s):

Packing Density ◽

Propagation Delay ◽

Single Chip ◽

Crosstalk Noise ◽

Metal Line ◽

Total Delay ◽

Interlayer Dielectric ◽

Low Dielectric ◽

Interconnect Delay ◽

Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2013p0255 ◽

2013 ◽

Author(s):

Sweta Pendyala ◽

Dave Albert ◽

Katherine Hawkins ◽

Michael Tenney

Keyword(s):

Deep Submicron ◽

Work Flow ◽

Localization Technique ◽

Characterization Techniques ◽

Capacitance Voltage ◽

Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

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Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0327 ◽

2007 ◽

Author(s):

Cha-Ming Shen ◽

Yen-Long Chang ◽

Lian-Fon Wen ◽

Tan-Chen Chuang ◽

Shi-Chen Lin ◽

...

Keyword(s):

Integrated Circuits ◽

Radio Frequency ◽

Failure Analysis ◽

Case Studies ◽

Mixed Mode ◽

Failure Mechanisms ◽

Deep Submicron ◽

Digital Logic ◽

Successful Approach ◽

Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

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A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0100 ◽

2014 ◽

Author(s):

Gwee Hoon Yen ◽

Ng Kiong Kay

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Flip Chip ◽

Fault Localization ◽

Cost Effective ◽

Fault Isolation ◽

Voltage Contrast ◽

Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

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Thermal Frequency Imaging: A New Application of Laser Voltage Imaging Applied on 40nm Technology

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0018 ◽

2011 ◽

Author(s):

Guillaume Celi ◽

Sylvain Dudit ◽

Thierry Parrassin ◽

Philippe Perdu ◽

Antoine Reverdy ◽

...

Keyword(s):

Charge Carrier ◽

Laser Beam ◽

Integrated Circuit ◽

Carrier Density ◽

Deep Submicron ◽

Charge Carrier Density ◽

Voltage Imaging ◽

A New Technique ◽

Scan Chain

Abstract For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

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