scholarly journals SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

2013 ◽  
pp. 181-195 ◽  
Author(s):  
Seokjoong Kim ◽  
Matthew R. Guthaus
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Array Architecture

AlInAs/GaInAs on InP HEMTs for low power supply voltage operation of high power-added efficiency microwave amplifiers

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  
Keyword(s):  
Low Power ◽  
High Power ◽  
Power Supply ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Power Added Efficiency ◽  
Microwave Amplifiers

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

A Low Power Low-Pass Fourth-Order Filter for WiMAX/LTE Receiver in CMOS 45nm Technology

2016 ◽  
Vol 26 (03) ◽  
pp. 1750048 ◽  
Author(s):  
Vida Orduee Niar ◽  
Gholamreza Zare Fatin
Keyword(s):  
Low Power ◽  
Fourth Order ◽  
Supply Voltage ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Power Filter ◽  
Order Filter ◽  
Source Follower ◽  
Low Pass ◽  
Circuit Technique

In this paper, a [Formula: see text]-[Formula: see text] low-pass and low power filter with tunable in-band attenuation for WiMAX/LTE receiver is presented. The fourth-order filter consists of two cascaded biquad stages. The source-follower (SF) stage is used as a key building block in these biquads. In this paper, we have presented a circuit technique to reduce the nonlinearity of the SF stage resulting from unmatched signal swings at the gate and source terminals of the input transistor. The proposed SF stage, is used for design of a linear biquad which is then utilized in a fourth-order Butterworth low-pass filter. The simulation results of the filter for bandwidth of 10 MHz show that the IIP3 of the filter is equal to 8.22[Formula: see text]dBm, in-band noise density is 100[Formula: see text]nV/[Formula: see text]Hz and power consumption is 5.9[Formula: see text]mW. The supply voltage of the filter is equal to 1[Formula: see text]V.

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

scholarly journals DVCC-based Low-power RF Filter with 32 nm CNFETs

2021 ◽  
Author(s):  
Shailendra Tripathi ◽  
Amit Mahesh Joshi
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Satellite Communication ◽  
Supply Voltage ◽  
Wide Band ◽  
Rf Receiver ◽  
Rf Filter ◽  
Low Supply Voltage ◽  
Differential Voltage Current Conveyor ◽  
Carbon Nanotube Fet

Abstract This work presents a wide-band active filter for RF receiver. The design uses Carbon Nanotube-FET (CNFET) based differential voltage current conveyor (DVCC) for the implementation of the proposed filter. The filter is designed to operate Ku-band frequencies (12-18 GHz), which is used in satellite communication. Additionally, CMOS based circuit and CNFET-based circuit for DVCC are compared for the performance evaluation. HSPICE simulations have been carried out to test the design aspects of the circuit. The CNFET-based circuit has better results in terms of 60 % reduction in the power consumption and about six times improvement in the bandwidth. The filter utilizes low supply voltage of 0.9 V and consumes 524 µW only. The proposed filter outperforms the existing CMOS-based designs which suggests its usage for low-power high-frequency analog circuits.

scholarly journals Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications.

2018 ◽  
Vol 7 (2.12) ◽  
pp. 205
Author(s):  
T Vasudeva Reddy ◽  
Dr B.K. Madhavi
Keyword(s):  
Low Power ◽  
High Performance ◽  
Supply Voltage ◽  
Process Variations ◽  
Primary Objective ◽  
Total Power ◽  
Threshold Region ◽  
Major Power ◽  
Low Power Circuits ◽  
Power Circuits

Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay. 

scholarly journals SUPPLY VOLTAGE CONTROL OF HALL SENSORS FOR LOW POWER MAGNETO-ELECTRIC SYSTEMS

2019 ◽  
Vol 2019 (52) ◽  
pp. 62-68
Author(s):  
K. Akynin ◽  
◽  
O. Antonov ◽  
V. Kireiev ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Voltage Control ◽  
Hall Sensors

scholarly journals Low Power AVLS-TSPC based 2/3 Pre-Scaler

2019 ◽  
Vol 9 (1) ◽  
pp. 6687-6693
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Signal ◽  
High Frequency Signal ◽  
Power Requirement ◽  
Fast Pace ◽  
Integer Division

The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.

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