Fabrication of n-ZnO/p-Si (100) and n-ZnO:Al/p-Si (100) Heterostructures and Study of Current–Voltage, Capacitance–Voltage and Room-Temperature Photoluminescence

2017 ◽  
Vol 47 (1) ◽  
pp. 879-886 ◽  
Author(s):  
M. A. H. Shah ◽  
M. K. R. Khan ◽  
A. M. M. Tanveer Karim ◽  
M. M. Rahman ◽  
M. Kamruzzaman
Keyword(s):  
Room Temperature ◽  
Room Temperature Photoluminescence ◽  
Current Voltage ◽  
Capacitance Voltage

Laser Engineering of Barrier Structures Based on Solid Solution ZnCdHgTe.

2002 ◽  
Vol 719 ◽  
Author(s):  
Galina Khlyap
Keyword(s):  
Room Temperature ◽  
Film Surface ◽  
Charge Carriers ◽  
Barrier Structure ◽  
Free Charge ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Laser Engineering ◽  
Charged Defects ◽  
Epilayer Surface

AbstractRoom-temperature electric investigations carried out in CO2-laser irradiated ZnCdHgTe epifilms revealed current-voltage and capacitance-voltage dependencies typical for the metal-semiconductor barrier structure. The epilayer surface studies had demonstrated that the cell-like relief has replaced the initial tessellated structure observed on the as-grown samples. The detailed numerical analysis of the experimental measurements and morphological investigations of the film surface showed that the boundaries of the cells formed under the laser irradiation are appeared as the regions of accumulation of derived charged defects of different type of conductivity supplying free charge carriers under the applied electric field.

scholarly journals Production and Electrical Properties of a CuZnAlMn(SMA)/p-Si Diode

2021 ◽  
Author(s):  
EMINE ALDIRMAZ ◽  
M. Güler ◽  
E. Güler
Keyword(s):  
Room Temperature ◽  
Schottky Contact ◽  
Phase Identification ◽  
Frequency Interval ◽  
Electrical Measurements ◽  
X Ray ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Type Semiconductor ◽  
Diode Current

Abstract In this study, the Cu-23.37%Zn-13.73%Al-2.92%Mn (at.%) alloy was used. Phase identification was performed with the Scanning electron microscope (SEM), and energy-dispersive X-ray (EDX). We observed in the austenite phase in Cu-23.37%Zn-13.73%Al-2.92%Mn (at.%) alloy. To produce a new Schottky diode, CuZnAlMn alloy was exploited as a Schottky contact on p-type semiconductor silicon substrate. To calculate the characteristics of the produced diode, current-voltage (I-V), capacitance-voltage (C-V) and conductance-voltage (G-V) analyzes were taken at room temperature (300 K), in the dark and under various lights. Using electrical measurements, the diode's ideality factor (n), barrier height (Φb), and other diode parameters were calculated. Besides, the conductance / capacitance-voltage (G/C-V) characteristics of the diode were studied and in a wide frequency interval at room temperature. Also, the capacitance and conductance values strongly ​​ rely on the frequency. From the present experimental results, the obtained diode can be used for optoelectronic devices.

Efficient Cu(In, Ga)Se2 Based Solar Cells Prepared by Electrodeposition

2003 ◽  
Vol 763 ◽  
Author(s):  
D. Guimard ◽  
N. Bodereau ◽  
J. Kurdi ◽  
J.F. Guillemoles ◽  
D. Lincot ◽  
...  
Keyword(s):  
Band Gap ◽  
Room Temperature ◽  
Open Circuit Voltage ◽  
Spectral Response ◽  
Deposition Process ◽  
Open Circuit ◽  
Response Analysis ◽  
Cell Parameters ◽  
Current Voltage ◽  
Capacitance Voltage

AbstractCuInSe2 and Cu(In, Ga)Se2 precursor layers have been prepared by electrodeposition, with morphologies suitable for device completion. These precursor films were transformed into photovoltaic quality films after thermal annealing without any post-additional vacuum deposition process. Depending on the preparation parameters annealed films with different band gaps between 1eV and 1.5 eV have been prepared. The dependence of resulting solar cell parameters has been investigated. The best efficiency achieved is about 10,2 % for a band gap of 1.45 eV. This device presents an open circuit voltage value of 740 mV, in agreement with the higher band gap value. Device characterisations (current-voltage, capacitance-voltage and spectral response analysis) have been performed. Admittance spectroscopy at room temperature indicates the presence of two acceptor traps at 0.3 and 0.43 eV from the valance band with density of the order of 2. 1017 cm-3 eV-1.

EFFECT OF SURFACE PASSIVATION ON CAPACITANCE–VOLTAGE CHARACTERISTICS OF Sn/p-Si SCHOTTKY CONTACTS

2011 ◽  
Vol 25 (04) ◽  
pp. 531-542
Author(s):  
CABİR TEMİRCİ ◽  
BAHRI BATI
Keyword(s):  
Chemical Treatment ◽  
Room Temperature ◽  
Surface Passivation ◽  
Anodic Oxide ◽  
Treatment Method ◽  
Schottky Contacts ◽  
Metal Insulator ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Effect Of Surface

We have fabricated the Sn/p-Si Schottky barrier diodes with the interfacial layer metal–insulator–semiconductor (D-MIS) and the surface passivation metal–semiconductor MS (D-MS) by the anodization or chemical treatment method. The current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the devices were measured at room temperature. We obtained that the excess capacitance (C0) value of the MIS Sn/p-Si diode with the anodic oxide layer of 16.88 pF and 0.12 pF for the MS Sn/p-Si ideal diode with the surface passivation by the anodization or chemical treatment method from reverse bias C–V characteristics. Thus, we have succeeded to diminish the excess capacitance value to the limit of 0.12 pF for the MS Sn/p-Si diode by using the anodization or chemical treatment method.

Schottky Barriers on p-GaN

1995 ◽  
Vol 395 ◽  
Author(s):  
N.I. Kuznetsov ◽  
E.V. Kalinina ◽  
V.A. Soloviev ◽  
V.A. Dmitriev
Keyword(s):  
Room Temperature ◽  
Current Flow ◽  
Thermal Evaporation ◽  
Chemical Vapor ◽  
Schottky Barriers ◽  
Flow Mechanism ◽  
Vacuum Thermal Evaporation ◽  
Forward Current ◽  
Current Voltage ◽  
Capacitance Voltage

ABSTRACTSchottky barriers were formed on p-GaN. p-GaN layers doped with Mg were grown by metalorganic chemical vapor deposition (MOCVD). 6H-SiC wafers were used as substrates. The barriers were made by vacuum thermal evaporation of Au. Capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the barriers were investigated. The concentration of the ionized acceptors in the p-layers was measured to be about ∼1017 cm−3. The barrier height was determined to be 2.48 eV by C - V measurements at room temperature. The forward current flow mechanism through the barriers is discussed.

Modeling and Simulations of Pd/n-ZnO Schottky Diode and its Comparison with Measurements

2009 ◽  
Vol 79-82 ◽  
pp. 1317-1320 ◽  
Author(s):  
S Faraz ◽  
Haida Noor ◽  
M. Asghar ◽  
Magnus Willander ◽  
Qamar-ul Wahab
Keyword(s):  
Schottky Diode ◽  
Room Temperature ◽  
Depletion Region ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Current Voltage Characteristics ◽  
Recombination Current ◽  
Experimental Values ◽  
Iv Curves ◽  
The Ideal

Modeling of Pd/ZnO Schottky diode has been performed together with a set of simulations to investigate its behavior in current-voltage characteristics. The diode was first fabricated and then the simulations were performed to match the IV curves to investigate the possible defects and their states in the bandgap. The doping concentration measured by capacitance-voltage is 3.4 x 1017 cm-3. The Schottky diode is simulated at room temperature and the effective barrier height is determined from current voltage characteristics both by measurements and simulations and it was found to be 0.68eV. The ideality factor obtained from simulated results is 1.06-2.04 which indicates that the transport mechanism is thermionic. It was found that the recombination current in the depletion region is responsible for deviation of experimental values from the ideal thermionic model deployed by the simulator.

Smart Heterostructures Based on Solid Solution ZnCdHgTe

2003 ◽  
Vol 785 ◽  
Author(s):  
Galina M. Khlyap ◽  
Petro G. Sydorchuk ◽  
Jacek Polit ◽  
Macej Oszwaldowsky
Keyword(s):  
Thin Films ◽  
Solid Solution ◽  
Spectral Range ◽  
Room Temperature ◽  
Signal Frequency ◽  
Applied Bias ◽  
Current Voltage ◽  
Wide Range ◽  
Capacitance Voltage ◽  
First Time

ABSTRACTCurrent – voltage (IVC) and capacitance – voltage (CVC) of heterostructures (Cd, Zn)Te/ZnCdHgTe are studied for the first time. Thin films ZnxCdyHg1-x-yTe were grown on monocrystalline (111) CdTe and ZnTe substrates by PLE technology. Deposition was carried out on substrates held at temperatures near 290 K. The thickness of investigated films was estimated to be about 5 μm. Electric characteristics of the as-grown structures were examined under T = 77–290 K in the wide range of applied bias. All investigated samples have demonstrated diode-like IVC and CVC under test signal frequency f = 1 kHz. Heterostructures CdTe/ZnCdHgTe have exhibited a room temperature photosensitivity in spectral range 0.50–0.65 μm.

GaN P-N Structures Fabricated by Mg ION Implantation

1998 ◽  
Vol 537 ◽  
Author(s):  
E.V. Kalinina ◽  
V.A. Solov'ev ◽  
A.S. Zubrilov ◽  
V.A. Dmitriev ◽  
A.P. Kovarsky
Keyword(s):  
Ion Implantation ◽  
Room Temperature ◽  
Implantation Dose ◽  
Electrical Characteristics ◽  
Scattered Electron ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Electron Beam Induced Current ◽  
P Type ◽  
Secondary Ion

AbstractIn this paper we report on the first GaN p-n diodes fabricated by Mg ion implantation doping of n-type GaN epitaxial layers. Ion implantation was performed at room temperature. Implantation dose ranged from 1013 to 2 × 1016 cm2. After implantation samples were annealed for 10-15 s at a wide temperature interval from 600°C to 1200°C in flowing N2 to form p-type layers. Secondary ion mass spectroscopy, scanning electron microscopy with electron beam induced current and back scattered electron modes as well as current-voltage and capacitance-voltage measurements were used to study structural and electrical characteristics of the Mg implanted p-n structures.

scholarly journals Effect of Annealing Atmosphere on the Diode Behaviour of ZnO/Si Heterojunction

2021 ◽  
Author(s):  
Sadia Muniza Faraz ◽  
Syed Riaz un Nabi Jafri ◽  
Zarreen Tajvar ◽  
Naveed ul Hassan Alvi ◽  
Qamar-ul Wahab ◽  
...  
Keyword(s):  
Ideality Factor ◽  
Room Temperature ◽  
Series Resistance ◽  
Zno Nanorods ◽  
Annealing Atmosphere ◽  
Electrical Characteristics ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Growth Method ◽  
Heterojunction Diodes

The effect of thermal annealing atmosphere on the electrical characteristics of Zinc oxide (ZnO) nanorods/p-Silicon (Si) diodes is investigated. ZnO nanorods are grown by low-temperature aqueous solution growth method and annealed in Nitrogen and Oxygen atmosphere. As-grown and annealed nanorods are studied by scanning electron microscopy (SEM) and photoluminescence (PL) spectroscopy. Electrical characteristics of ZnO/Si heterojunction diodes are studied by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. Improvements in rectifying behaviour, ideality factor, carrier concentration, and series resistance are observed after annealing. The ideality factor of 4.4 for as-grown improved to 3.8 and for Nitrogen and Oxygen annealed improved to 3.5 nanorods diodes. The series resistances decreased from 1.6 to 1.8 times after annealing. An overall improved behaviour is observed for oxygen annealed heterojunction diodes. The study suggests that by controlling the ZnO nanorods annealing temperatures and atmospheres the electronic and optoelectronic properties of ZnO devices can be improved.

Nanoindentation as a Tool for Formation of Thin Film-Based Barrier Structures

2005 ◽  
Vol 864 ◽  
Author(s):  
H. Khlyap ◽  
P. Sydorchuk
Keyword(s):  
Room Temperature ◽  
Far Infrared ◽  
Point Of View ◽  
Surface Barrier ◽  
Defect Engineering ◽  
High Quality ◽  
Laser Technology ◽  
Current Voltage ◽  
Capacitance Voltage ◽  
Selection Of

AbstractA2B6 semiconductors and their solid solutions (ZnSe, ZnTe, CdTe, ZnCdHgTe) are matter of choice for near- and far-infrared optoelectronics. The importance of maximally reduced degree of defectness for these materials is not subjected to discussion. However, preparation of high quality barrier structures based on these compounds by means of MBE, laser technology or liquid phase technique is not always successful due to lattice parameters mismatch. At the same time, good selection of a proper buffer layer may also pose some unavoidable problems. From this point of view the nanoindentation as a tool of defect engineering can be effective for fabrication of surface barrier structures. The first experimental results and numerical simulation of experimental data obtained under investigation of nanoindentation effect on electric characteristics (in particular, current – voltage (I-V) and capacitance – voltage (C-V)) of ZnCdHgTe thin films and ZnCdHgTe/Cd(Zn)Te heterostructures at the room temperature are presented.

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