Design Flow to Evaluate the Performance of Ring Oscillator PUFs on FPGAs

Author(s):  
Macarena C. Martinez-Rodriguez ◽  
Eros Camacho-Ruiz ◽  
Santiago Sanchez-Solano ◽  
Piedad Brox
Keyword(s):  
2015 ◽  
Vol 24 (07) ◽  
pp. 1550104 ◽  
Author(s):  
Sarang Kazeminia ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei

A straightforward methodology of optimizing ring-oscillator phase-locked loops (PLLs) is organized for integer-N PLLs. Then, a brief 4-step design flow is concluded to implicitly quantize the loop components for optimized loop stability. Theoretical analysis confirms that the ratio of more than 20 is required for loop filter's capacitors to yield at least 65° degrees phase margin. A wide-range voltage controlled oscillator (VCO) is proposed which is continuously controlled through two fast and slow response paths. The fast-response path improves RMS jitter due to decreasing loop delay and the slower one is an adaptive bias tuning loop, utilized to reduce the power consumption at lower operating frequencies. The RMS jitter of around 2 ps and 0.35 ps at 250 MHz and 4 GHz operating frequencies are obtained, respectively, where the 1.8 V supply voltage is subjected to about 60 mV peak-to-peak noise and reference clock suffers from 12 ps peak-to-peak jitter. Power consumption is reduced from 12.6–4 mW at 250 MHz operating frequency when the adaptive bias scheme is applied. Furthermore, simulation results confirm 35% and 50% improvement in RMS and peak-to-peak jitter at 250 MHz operating frequency, respectively, when the ratio of capacitances is increased from 10 to 20 within the loop filter. The proposed PLL can be implemented in 170 μm × 250 μm active area in 0.18 μm CMOS process.


Author(s):  
Mike Bruce ◽  
Rama R. Goruganthu ◽  
Shawn McBride ◽  
David Bethke ◽  
J.M. Chin

Abstract For time resolved hot carrier emission from the backside, an alternate approach is demonstrated termed single point PICA. The single point approach records time resolved emission from an individual transistor using time-correlated-single-photon counting and an avalanche photo-diode. The avalanche photo-diode has a much higher quantum efficiency than micro-channel plate photo-multiplier tube based imaging cameras typically used in earlier approaches. The basic system is described and demonstrated from the backside on a ring oscillator circuit.


2018 ◽  
Author(s):  
Satish Kodali ◽  
Liangshan Chen ◽  
Yuting Wei ◽  
Tanya Schaeffer ◽  
Chong Khiam Oh

Abstract Optical beam induced resistance change (OBIRCH) is a very well-adapted technique for static fault isolation in the semiconductor industry. Novel low current OBIRCH amplifier is used to facilitate safe test condition requirements for advanced nodes. This paper shows the differences between the earlier and novel generation OBIRCH amplifiers. Ring oscillator high standby leakage samples are analyzed using the novel generation amplifier. High signal to noise ratio at applied low bias and current levels on device under test are shown on various samples. Further, a metric to demonstrate the SNR to device performance is also discussed. OBIRCH analysis is performed on all the three samples for nanoprobing of, and physical characterization on, the leakage. The resulting spots were calibrated and classified. It is noted that the calibration metric can be successfully used for the first time to estimate the relative threshold voltage of individual transistors in advanced process nodes.


Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.


Author(s):  
Jeffery P. Huynh ◽  
Joseph P. Shannon ◽  
Richard W. Johnson ◽  
Mike Santana ◽  
Thomas Y. Chu ◽  
...  

Abstract Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.


2009 ◽  
Vol 4 (3) ◽  
Author(s):  
I. Venner ◽  
J. Husband ◽  
J. Noonan ◽  
A. Nelson ◽  
D. Waltrip

In response to rapid population growth as well as to address the nutrient reduction goals for the Chesapeake Bay established by the Virginia Department of Environmental Quality (VDEQ), the Hampton Roads Sanitation District (HRSD) initiated the York River Treatment Plant (YRTP) Expansion Phase 1 project. The existing YRTP is a conventional step-feed activated sludge plant and is rated for an average daily design flow of 57 million liters per day (MLD). This project proposes to expand the existing treatment capacity to 114 MLD and to reduce the nutrients discharged to the York River, a tributary for the Chesapeake Bay. In order to meet the effluent limits set by the VDEQ, a treatment upgrade to limit of technology (LOT) or enhanced nutrient removal (ENR) was required. Malcolm Pirnie worked with HRSD and the VDEQ to develop and evaluate ENR process alternatives to achieve the required effluent limits with the goal of determining the most reliable and cost effective alternative to achieve the aggressive nutrient reduction goals. This paper will highlight the key issues in determining the most desirable treatment process considering both economic and non-economic factors.


1990 ◽  
Vol 22 (7-8) ◽  
pp. 53-60 ◽  
Author(s):  
B. Rabinowitz ◽  
T. D. Vassos ◽  
R. N. Dawson ◽  
W. K. Oldham

A brief review of recent developments in biological nitrogen and phosphorus removal technology is presented. Guidelines are outlined of how current understanding of these two removal mechanisms can be applied in the upgrading of existing wastewater treatment plants for biological nutrient removal. A case history dealing with the upgrading of the conventional activated sludge process located at Penticton, British Columbia, to a biological nutrient removal facility with a design flow of 18,200 m3/day (4.0 IMGD) is presented as a design example. Process components requiring major modification were the headworks, bioreactors and sludge handling facilities.


Author(s):  
A. L. Stempkovskiy ◽  
◽  
D. V. Telpukhov ◽  
A. I. Demeneva ◽  
T. D. Zhukova ◽  
...  

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