The Impact of Substrates on the Performance of Top-Gate p-Ga203 Field-Effect Transistors: Record High Drain Current of 980 mA/mm on Diamond

Nonlinearity Analysis of Quantum Capacitance and its Effect on Nano-Graphene Field Effect Transistor characteristics

10.21203/rs.3.rs-893064/v1 ◽

2021 ◽

Author(s):

MUNINDRA MUNINDRA ◽

DEVA NAND

Keyword(s):

Field Effect ◽

Field Effect Transistors ◽

Drain Current ◽

Charge Carrier Concentration ◽

Single Layer Graphene ◽

Quantum Capacitance ◽

Large Area ◽

Source Voltage ◽

Current Calculation ◽

The Impact

Abstract A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene field effect transistors (GFETs) with large area graphene is presented in which the quantum mechanical density gradient method is utilised. The basic device physics of the two-dimensional (2D) graphene channel is studied analytically. This modeling leads to the precise drain current calculation of the GFETs. The drain current calculation for GFETs starts from charge carrier concentration, its density of states and quantum capacitance(QC). QC depends on the channel voltage as a function of gate to source voltage Vgs and drain to source voltage Vds primarily. The formulation of the drain current with velocity saturation has been done by the Monte Carlo simulation method. The performance of the analytical GFETs model is present the precise values of QC, its impact on drain current and transfer as well as output characteristics. The impact of QC at nanometer technology adds the nonlinearity to characteristics curves. The proposed method provides better results as compared with the previous analytical and simulated results.

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Preparation of integrated chemical sensors using commercial VLSI technology

Canadian Journal of Chemistry ◽

10.1139/v87-181 ◽

1987 ◽

Vol 65 (5) ◽

pp. 1072-1078 ◽

Cited By ~ 3

Author(s):

Paul G. Glavina ◽

D. Jed Harrison

Keyword(s):

Chemical Sensors ◽

Linear Response ◽

Field Effect ◽

Field Effect Transistors ◽

Microelectrode Arrays ◽

Drain Current ◽

Cyclic Voltammetric ◽

Design Rules ◽

Vlsi Technology ◽

Commercial Technology

The fabrication of ion sensitive field effect transistors (ISFET) and microelectrode arrays for use as chemical sensors using a commercial CMOS fabrication process is described. The commercial technology is readily available through the Canadian Microelectronics Corporation; however, several of the recommended design rules must be ignored in preparing chemical sensors using this process. The ISFET devices show near theoretical response to K+ in aqueous solution (55 mV slope) when coated with a K+ sensitive membrane. An extended gate ion sensitive device is presented which offers advantages in encapsulation of ISFET sensors. The source-drain current of both devices show a linear response to log [Formula: see text] in contrast to ISFETs previously reported that have high internal lead resistances. Al and poly-Si microelectrode arrays are fabricated commercially and then Pt is electrodeposited on the microelectrodes. The resulting arrays show good cyclic voltammetric response to Fe(CN)64− and Ru(NH3)63+ and are relatively durable.

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AlGaN/GaN Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistors (MOSHFETs) with the Delta-Doped Barrier Layer

MRS Proceedings ◽

10.1557/proc-743-l9.11 ◽

2002 ◽

Vol 743 ◽

Author(s):

Z. Y. Fan ◽

J. Li ◽

J. Y. Lin ◽

H. X. Jiang ◽

Y. Liu ◽

...

Keyword(s):

Metal Oxide ◽

Field Effect ◽

Field Effect Transistors ◽

Cutoff Frequency ◽

Drain Current ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Semiconductor Heterostructure ◽

Heterostructure Field Effect Transistors ◽

Gate Control

ABSTRACTThe fabrication and characterization of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with the δ-doped barrier are reported. The incorporation of the SiO2 insulated-gate and the δ-doped barrier into HFET structures reduces the gate leakage and improves the 2D channel carrier mobility. The device has a high drain-current-driving and gate-control capabilities as well as a very high gate-drain breakdown voltage of 200 V, a cutoff frequency of 15 GHz and a maximum frequency of oscillation of 34 GHz for a gate length of 1 μm. These characteristics indicate a great potential of this structure for high-power-microwave applications.

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Temporal Changes in Source–Drain Current for Organic Field-Effect Transistors Caused by Dipole on Insulator Surface

Applied Physics Express ◽

10.1143/apex.1.061801 ◽

2008 ◽

Vol 1 ◽

pp. 061801 ◽

Cited By ~ 14

Author(s):

Kouji Suemori ◽

Misuzu Taniguchi ◽

Sei Uemura ◽

Manabu Yoshida ◽

Satoshi Hoshino ◽

...

Keyword(s):

Field Effect ◽

Field Effect Transistors ◽

Drain Current ◽

Temporal Changes ◽

Organic Field Effect Transistors ◽

Insulator Surface

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Influence of work function variation of metal gates on fluctuation of sub-threshold drain current for fin field-effect transistors with undoped channels

Japanese Journal of Applied Physics ◽

10.7567/jjap.53.04ec11 ◽

2014 ◽

Vol 53 (4S) ◽

pp. 04EC11 ◽

Cited By ~ 11

Author(s):

Takashi Matsukawa ◽

Yongxun Liu ◽

Kazuhiko Endo ◽

Junichi Tsukada ◽

Hiromi Yamauchi ◽

...

Keyword(s):

Work Function ◽

Field Effect ◽

Field Effect Transistors ◽

Drain Current ◽

Metal Gates

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Line-Edge Roughness from Extreme Ultraviolet Lithography to Fin-Field-Effect-Transistor: Computational Study

Micromachines ◽

10.3390/mi12121493 ◽

2021 ◽

Vol 12 (12) ◽

pp. 1493

Author(s):

Sang-Kon Kim

Keyword(s):

Field Effect ◽

Extreme Ultraviolet ◽

Field Effect Transistors ◽

Computational Study ◽

Drain Current ◽

Extreme Ultraviolet Lithography ◽

Line Edge Roughness ◽

Stochastic Fluctuation ◽

Ultraviolet Lithography ◽

Edge Roughness

Although extreme ultraviolet lithography (EUVL) has potential to enable 5-nm half-pitch resolution in semiconductor manufacturing, it faces a number of persistent challenges. Line-edge roughness (LER) is one of critical issues that significantly affect critical dimension (CD) and device performance because LER does not scale along with feature size. For LER creation and impacts, better understanding of EUVL process mechanism and LER impacts on fin-field-effect-transistors (FinFETs) performance is important for the development of new resist materials and transistor structure. In this paper, for causes of LER, a modeling of EUVL processes with 5-nm pattern performance was introduced using Monte Carlo method by describing the stochastic fluctuation of exposure due to photon-shot noise and resist blur. LER impacts on FinFET performance were investigated using a compact device method. Electric potential and drain current with fin-width roughness (FWR) based on LER and line-width roughness (LWR) were fluctuated regularly and quantized as performance degradation of FinFETs.

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Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

Nanomaterials ◽

10.3390/nano11113121 ◽

2021 ◽

Vol 11 (11) ◽

pp. 3121

Author(s):

Monica La Mura ◽

Patrizia Lamberti ◽

Vincenzo Tucci

Keyword(s):

High Frequency ◽

Communication Systems ◽

Field Effect ◽

Field Effect Transistor ◽

Field Effect Transistors ◽

Channel Length ◽

Geometrical Parameters ◽

Effect Transistor ◽

Rf Performance ◽

The Impact

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

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Insight into Channel Conduction Mechanisms of 4H-SiC(0001) MOSFET Based on Temperature-Dependent Hall Effect Measurement

Materials Science Forum ◽

10.4028/www.scientific.net/msf.1004.620 ◽

2020 ◽

Vol 1004 ◽

pp. 620-626

Author(s):

Hironori Takeda ◽

Mitsuru Sometani ◽

Takuji Hosoi ◽

Takayoshi Shimura ◽

Hiroshi Yano ◽

...

Keyword(s):

Hall Effect ◽

Field Effect ◽

Elevated Temperatures ◽

Field Effect Transistors ◽

Free Carrier ◽

Oxide Semiconductor ◽

Thermal Excitation ◽

Temperature Dependent ◽

Conduction Mechanisms ◽

The Impact

Temperature-dependent Hall effect measurements were conducted to investigate the channel conduction mechanisms of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). This method allows us to discriminate the impact of the density of mobile (free) carriers in the inversion channels and their net mobility on the performance of SiC MOSFETs. It was found that, while the free carrier ratio of SiC MOSFETs with conventional gate oxides formed by dry oxidation is below 4% at 300 K, increasing the free carrier ratio due to thermal excitation of trapped electrons from SiO2/SiC interfaces leads to an unusual improvement in the field-effect mobility of SiC MOSFETs at elevated temperatures. Specifically, a significant increase in free carrier density surpasses the mobility degradation caused by phonon scattering for thermally grown SiO2/SiC interfaces. It was also found that, although nitrogen incorporation in SiO2/SiC interfaces increases the free carrier ratio typically up to around 30%, introduction of an additional scattering factor associated with interface nitridation compensates for the moderate amount of thermally generated mobile carriers at high temperatures, indicating a fundamental drawback of nitridation of SiO2/SiC interfaces. On the basis of these findings, we discuss the channel conduction mechanisms of SiC MOSFETs.

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High Performance Organic Field-Effect Transistors and Integrated Inverters

MRS Proceedings ◽

10.1557/proc-665-c7.5 ◽

2001 ◽

Vol 665 ◽

Cited By ~ 16

Author(s):

A. Ullmann ◽

J. Ficker ◽

W. Fix ◽

H. Rost ◽

W. Clemens ◽

...

Keyword(s):

Field Effect ◽

High Performance ◽

Field Effect Transistors ◽

Low Cost ◽

Drain Current ◽

Organic Field Effect Transistors ◽

Metal Contacts ◽

Gate Electrodes ◽

Polymer Semiconductors ◽

Set Up

ABSTRACTIntegrated plastic circuits (IPCs) will become an integral component of future low cost electronics. For low cost processes IPCs have to be made of all-polymer Transistors. We present our recent results on fabrication of Organic Field-Effect Transistors (OFETs) and integrated inverters. Top-gate transistors were fabricated using polymer semiconductors and insulators. The source-drain structures were defined by standard lithography of Au on a flexible plastic film, and on top of these electrodes, poly(3-alkylthiophene) (P3AT) as semiconductor, and poly(4-hydroxystyrene) (PHS) as insulator were homogeneously deposited by spin-coating. The gate electrodes consist of metal contacts. With this simple set-up, the transistors exhibit excellent electric performance with a high source-drain current at source - drain and gate voltages below 30V. The characteristics show very good saturation behaviour for low biases and are comparable to results published for precursor pentacene. With this setup we obtain a mobility of 0.2cm2/Vs for P3AT. Furthermore, we discuss organic integrated inverters exhibiting logic capability. All devices show shelf-lives of several months without encapsulation.

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