Development of Novel High Density System Integration Solutions in FOWLP-Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages

2017 ◽  
Author(s):  
Andre Cardoso ◽  
Leonor Dias ◽  
Elisabete Fernandes ◽  
Alberto Martins ◽  
Abel Janeiro ◽  
...  
Keyword(s):  
System Integration ◽  
High Density ◽  
Wafer Level

High Density Interposer – Challenges and Opportunities

2015 ◽  
Vol 2015 (1) ◽  
pp. 000046-000049 ◽  
Author(s):  
Mathias Boettcher ◽  
Frank Windrich ◽  
M-J. Wolf
Keyword(s):  
System Integration ◽  
Functional System ◽  
High Density ◽  
Wafer Level ◽  
Active Components ◽  
Wide Range ◽  
Challenges And Opportunities ◽  
High Level ◽  
Silicon Vias ◽  
System Miniaturization

Within “More than Moore” concepts interposer based packaging technologies, known as 2.5D/3D wafer level system integration, open up a wide range of miniaturized multi-functional system solutions. Pending of the final application dedicated interposer concepts have been developed for grabbing multiple active components, fabricated by different suppliers, using different technologies and materials, e.g. sensors, logic, radio frequency (RF) and memory-ICs, as well as passive devices, including antennas. In many cases the application of high density wiring, micro pillar (μ-pillar) interconnects as well as through silicon vias (TSVs) are required. Finally the interposer needs to provide the mechanical basement for system packages. In order to support system miniaturization and extension of system performance on one hand and to meet costs and time to market challenges on the other hand the development of modular interposer concepts as well as the application of dedicated basic interposer technologies is of high interest for R&D, prototyping and small volume applications. A short outline of high density interposer technologies developed and available at Fraunhofer IZM on 300mm substrates will be presented. Starting with a brief discussion of basic elements of interposers, several technology concepts developed and validated for high density interposer applications will be described. Challenges related to μ-pillar applications and high density wiring will be addressed and generic results will be presented. A high level comparison of challenges and opportunities will be shown and discussed. A brief outlook of future development work for system applications will be given.

Thin Die Fabrication and Applications to Wafer Level System Integration

2016 ◽  
pp. 237-285 ◽  
Author(s):  
Doug C. H. Yu ◽  
Wen-Chih Chiou ◽  
Chih Hang Tung
Keyword(s):  
System Integration ◽  
Level System ◽  
Wafer Level

Ultra-High-Density Interconnect Enabled by Hybrid Bonding for Heterogeneous Integration: Interfacial Characteristics

2021 ◽  
Author(s):  
Mei-Chien Lu
Keyword(s):  
Performance Metrics ◽  
High Volume ◽  
Image Sensor ◽  
Structure Design ◽  
High Density ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Bonding Area ◽  
The Impact ◽  
Interfacial Characteristics

Abstract Hybrid bonding has been explored for more than a decade and implemented recently in high volume production at wafer-to-wafer level for image sensor applications to enable high performance chip-stacking architectures with ultra-high-density chip-to-chip interconnect. The feasibility of sub-micron hybrid bond pitch leading to ultra-high-density chip-to-chip interconnect has been demonstrated due to the elimination of solder bridging issues from microbump method. Hybrid bonding has also been actively considered for logic and memory chip-stacking, chiplets, and heterogeneous integration in general but encountering additional challenges for bonding at die-to-wafer or die-to-die level. Overlay precision, throughput, wafer dicing are among the main causes. Widening the process margin against overlay error by designing innovative hybrid bonding pad structure is highly desirable. This work proposes a method to evaluate these hybrid bonding pad structure designs and to assess the potential performance metrics by analyzing interfacial characteristics at design phase. The bonding areas and ratios of copper-copper, copper-dielectric, and dielectric-dielectric are the proposed key parameters. The correlation between bonding area ratios and overlay errors can provide insights on the sensitivity to process margins. Nonetheless, the impact of copper recess or protrusion associated with bonding area ratios are also highlighted. The proposed method is demonstrated by examining and analyzing the hybrid bonding pad structure design concepts from a few cases reported in literatures as examples. Concerns are identified for elaboration in future designs and optimizations.

Development of High Density RDL Technologies for Panel Level Processing

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000284-000313
Author(s):  
Lars Böttcher ◽  
S. Karaszkiewicz ◽  
F. Schein ◽  
R. Kahle ◽  
A. Ostmann
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
High Density ◽  
Organic Films ◽  
High Yield ◽  
Wafer Level ◽  
Final Size ◽  
Process Yield ◽  
Cu Pillar ◽  
Thin Organic Films ◽  
Advanced Packaging

Advanced packaging technologies like wafer-level fan-out and 3D System-in-Packages (SIPs) are rapidly penetrating the market of electronic components. A recent trend to reduce cost is the extension of processes to large manufacturing formats, called Panel Level Packaging (PLP). In a consortium of German partners from industry and research advanced technologies for PLP are developed. The project aims for an integrated process flow for SIPs with chips embedded into an organic laminate matrix. At first dies with Cu pillar structures are placed into openings of a laminate frame layer with very low coefficient of thermal expansion (CTE). They are embedded by vacuum lamination of thin organic films, filling the very small gap down to 15 μm between chips and frame. The frame provides alignment marks for a local registration of following processes. The ridged frame limits die shift during embedding and gives a remarkable handling robustness. Developments are initially performed on a 305×256mm2 panel format, aiming for a final size of 610×615 mm2. On the top side of embedded chips, a 20μm dielectric film is applied. The goal is to avoid additional via formation and to realize a direct connection between the Cu pillar of the die and the RDL The RDL formation is based on semi-additive processing. Therefore a Ti or TiW barrier and Cu seed layer is sputtered. Subsequently a 7μm photoresist is applied and exposed by a newly developed Direct Imaging (DI) system. Lines and spaces of 4μm were achieved with high yield. In the following, Cu is simultaneously electroplated for the via contacts and interconnects traces. Finally, the photo resist is stripped and the TiW barrier and Cu seed layers are etched. The goal of the development is to provide a technology for a high-density RDL formation on large panel sizes. The paper will discuss the new developments in detail, e.g. the influence of most significant process parameters, like lithographical resolution, minimum via diameter and the placement and alignment accuracy on overall process yield.

Cost-Effective Precision 3D Glass Microfabrication for Advanced Packaging Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000791-000810
Author(s):  
Jeb Flemming ◽  
Roger Cook ◽  
Kevin Dunn ◽  
James Gouker
Keyword(s):  
Cost Effective ◽  
High Density ◽  
Consumer Electronics ◽  
Liquid Crystal Polymers ◽  
Portable Devices ◽  
Signal Loss ◽  
Wafer Level ◽  
Advanced Packaging ◽  
And Performance ◽  
Optical Waveguiding

Today's packaging has become the limiting element in system cost and performance for IC development. Assembly and packaging technologies have become primary differentiators for manufactures of consumer electronics and the main enabler of small IC product development. Traditional packaging approaches to address the needs in these “High Density Portable” devices, including FR4, liquid crystal polymers, and Low Temperature Co-Fire Ceramics, are running into fundamental limits in packaging layer thinness, high density interconnects (HDI) size and density, and do not present solutions to in-package thermal management, and optical waveguiding. In this talk, 3D Glass Solutions will present on our efforts to create advanced microelectronic packing solutions using our APEX™ Glass ceramic which offers a single material capable of being simultaneously used for ultra-HDI through glass vias (TGVs), optical waveguiding, and in-package microfluidic cooling. In this talk we will discuss our latest results in wafer-level microfabrication of packaging solutions. We will present on our efforts for creating copper filled vias, surface metallization, and passivation. Furthermore, we will present our efforts in exploring this material to produce (1) ultra-HDI glass interposers, with TGVs as small as 12 microns, with 14 micron center –to-center, (2) advanced RF packages with unique surface architectures designed to minimize signal loss, and (3) creating wave guiding structures in HDI packages.

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

2013 ◽  
Vol 2013 (1) ◽  
pp. 000447-000451 ◽  
Author(s):  
Michael Vincent ◽  
Doug Mitchell ◽  
Jason Wright ◽  
Yap Weng Foong ◽  
Alan Magnus ◽  
...  
Keyword(s):  
System Integration ◽  
System Performance ◽  
Electrical Characterization ◽  
Emerging Technology ◽  
Volumetric Efficiency ◽  
Wafer Level ◽  
Novel Technologies ◽  
3D Packaging ◽  
Packaging Space ◽  
On Chip

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

Packaging without the Package - A More Holistic Moore's Law

2017 ◽  
Vol 2017 (S1) ◽  
pp. 1-40
Author(s):  
Subramanian S. Iyer (Subu)
Keyword(s):  
System Integration ◽  
System Level ◽  
Heterogeneous Integration ◽  
Power Performance ◽  
Wafer Level ◽  
Innovative Materials ◽  
Barrier To Entry ◽  
On Chip ◽  
Market Consolidation ◽  
Conventional Systems

Silicon features have scaled by over 1500X for over six decades, and with the adoption of innovative materials delivered better power-performance, density and till recently, cost per function, almost every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. However, as SoCs have become bigger and more complex, the Non-Recurring Engineering (NRE) Charge and time to market have both ballooned out of control leading to ever increasing market consolidation. We need to address this problem through novel methods of system Integration. With the well-documented slowing down of scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging itself is undergoing a transformation that focuses on overall system performance through integration rather than on packaging individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. More importantly it will allow us to re-architect systems in a very significant way. This transformation is already under way with 3-D stacking of dies, Wafer level fan-out processing, and will evolve to make heterogeneous integration the backbone of a new SoC methodology, extending to integrate entire Systems on Wafers (SoWs). We will describe the technology we use and the results to-date. This has implications in redefining the memory hierarchy in conventional systems and in neuromorphic systems. We extend these concepts to flexible and biocompatible electronics.

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