Challenges and approaches of ultra-fine pitch Cu pillar assembly on organic substrate using wafer level underfill

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

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Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

International Symposium on Microelectronics ◽

10.4071/isom-2012-tp61 ◽

2012 ◽

Vol 2012 (1) ◽

pp. 000455-000463 ◽

Cited By ~ 2

Author(s):

Yasumitsu Orii ◽

Kazushige Toriyama ◽

Sayuri Kohara ◽

Hirokazu Noma ◽

Keishi Okamoto ◽

...

Keyword(s):

Flip Chip ◽

Organic Substrate ◽

Stress Tests ◽

Cross Sectional ◽

Current Stress ◽

Barrier Layers ◽

Cu Pillar ◽

Fine Pitch ◽

Cu Pillar Bump ◽

Cu Dissolution

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

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Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

International Symposium on Microelectronics ◽

10.4071/isom-2011-wp5-paper4 ◽

2011 ◽

Vol 2011 (1) ◽

pp. 000828-000836

Author(s):

Yasumitsu Orii ◽

Kazushige Toriyama ◽

Sayuri Kohara ◽

Hirokazu Noma ◽

Keishi Okamoto ◽

...

Keyword(s):

Aging Process ◽

Flip Chip ◽

Fem Simulation ◽

Organic Substrate ◽

Organic Substrates ◽

Cross Sectional ◽

Pillar Height ◽

Cu Pillar ◽

Fine Pitch ◽

Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

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Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2021.19132 ◽

2021 ◽

Vol 21 (5) ◽

pp. 2949-2958

Author(s):

Xuan Luc Le ◽

Han Eul Lee ◽

Sung-Hoon Choa

Keyword(s):

Deformation Behavior ◽

Solder Ball ◽

Microelectromechanical Systems ◽

Wafer Level ◽

Silicon Oxide Layer ◽

Cu Pillar ◽

Fine Pitch ◽

Cu Pillar Bump ◽

Vertical Probe ◽

Interconnection Structure

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.

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Design of New Au–NiCo MEMS Vertical Probe for Fine-Pitch Wafer-Level Probing

Crystals ◽

10.3390/cryst11050485 ◽

2021 ◽

Vol 11 (5) ◽

pp. 485

Author(s):

Xuan Luc Le ◽

Sung-Hoon Choa

Keyword(s):

Contact Stress ◽

Carrying Capacity ◽

Deformation Behavior ◽

Solder Ball ◽

Wafer Level ◽

Wafer Level Packaging ◽

Cu Pillar ◽

Fine Pitch ◽

Stress And Deformation ◽

Vertical Probe

As fine-pitch 3D wafer-level packaging becomes more popular in semiconductor industries, wafer-level prebond testing of various interconnect structures has become increasingly challenging. Additionally, improving the current-carrying capacity (CCC) and minimizing damage to the probe and micro-interconnect structures are very important issues in wafer-level testing. In this study, we propose an Au–NiCo MEMS vertical probe with an enhanced CCC to efficiently reduce the damage to the probe and various interconnect structures, including a solder ball, Cu pillar microbump, and TSV. The Au–NiCo probe has an Au layer inside the NiCo and an Au layer outside the surface of the NiCo probe to reduce resistivity and contact stress. The current-carrying capacity, contact stress, and deformation behavior of the probe and various interconnect structures were evaluated using numerical analyses. The Au–NiCo probe had a 150% higher CCC than the conventional NiCo probe. The maximum allowable current capacity of the 5000 µm-long Au–NiCo probe was 750 mA. The Au–NiCo probe exhibited less contact force and stress than the NiCo probe. The Au–NiCo probe also produced less deformation of various interconnect structures. These results indicate that the proposed Au–NiCo probe will be a prospective candidate for advanced wafer-level testing, with better probing efficiency and higher test yield and reliability than the conventional vertical probe.

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Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging

Micromachines ◽

10.3390/mi12030295 ◽

2021 ◽

Vol 12 (3) ◽

pp. 295

Author(s):

Pao-Hsiung Wang ◽

Yu-Wei Huang ◽

Kuo-Ning Chiang

Keyword(s):

Finite Element ◽

Thermal Cycling ◽

Glass Substrate ◽

High Speed ◽

Coefficient Of Thermal Expansion ◽

Three Dimensional ◽

Design Parameters ◽

Time To Failure ◽

Wafer Level ◽

Fine Pitch

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

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