The impact of clock gating schemes on the power dissipation of synthesizable register files

2004 ◽  
Author(s):  
M. Mueller ◽  
A. Wortmann ◽  
S. Simon ◽  
M. Kugel ◽  
T. Schoenauer
Keyword(s):  
Power Dissipation ◽  
Clock Gating ◽  
Register Files ◽  
The Impact

Direct Outer Ring Cooling of a High Speed Jet Engine Mainshaft Ball Bearing: Experimental Investigation Results

2010 ◽  
Author(s):  
Peter Gloeckner ◽  
Klaus Dullenkopf ◽  
Michael Flouros
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Ball Bearing ◽  
Operating Conditions ◽  
Outer Ring ◽  
Outer Diameter ◽  
Propulsion Systems ◽  
Jet Engine ◽  
Power Loss Reduction ◽  
The Impact

Operating conditions in high speed mainshaft ball bearings applied in new aircraft propulsion systems require enhanced bearing designs and materials. Rotational speeds, loads, demands on higher thrust capability, and reliability have increased continuously over the last years. A consequence of these increasing operating conditions are increased bearing temperatures. A state of the art jet engine high speed ball bearing has been modified with an oil channel in the outer diameter of the bearing. This oil channel provides direct cooling of the outer ring. Rig testing under typical flight conditions has been performed to investigate the cooling efficiency of the outer ring oil channel. In this paper the experimental results including bearing temperature distribution, power dissipation, bearing oil pumping and the impact on oil mass and parasitic power loss reduction are presented.

scholarly journals ZTC bias point of advanced fin based device: The importance and exploration

2015 ◽  
Vol 28 (3) ◽  
pp. 393-405 ◽  
Author(s):  
Sushanta Mohapatra ◽  
Kumar Pradhan ◽  
Prasanna Sahu
Keyword(s):  
Power Dissipation ◽  
Temperature Compensation ◽  
Performance Metrics ◽  
Zero Temperature ◽  
Sweet Spot ◽  
Static Power ◽  
20 Nm ◽  
Bias Point ◽  
The Impact ◽  
Present Understanding

The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.

Role of Through Silicon Via in 3D Integration: Impact on Delay and Power

2020 ◽  
pp. 2150051
Author(s):  
Shivangi Chandrakar ◽  
Deepika Gupta ◽  
Manoj Kumar Majumder
Keyword(s):  
Power Dissipation ◽  
Three Dimensional ◽  
Propagation Delay ◽  
Model Parameters ◽  
3D Integration ◽  
Coupling Behavior ◽  
Power Delay Product ◽  
Silicon Vias ◽  
The Impact

The metal–semiconductor (MES)-based through silicon vias (TSV) has provided attractive solutions over conventional metal–insulator–semiconductor (MIS) TSVs in recent three-dimensional (3D) integration. This paper aims a comprehensive performance analysis of MIS and MES structures considering different TSV shapes such as cylindrical, tapered, annular, and square. At 32[Formula: see text]nm technology, a CMOS-based coupled driver-via-load (DVL) setup is introduced wherein each via is represented an equivalent RLGC model of MIS- and MES-based TSV shapes. The proposed electrical model accurately considers the impact of micro bump and inter-metal dielectric (IMD) effects at 32[Formula: see text]nm technology as per the fabrication house. A 3D electromagnetic (EM) structural wave simulation is performed to validate the RLGC model parameters of different TSV structures for an operating frequency of up to 20[Formula: see text]GHz. The proposed DVL setup is used to analyze the propagation delay, power dissipation, and dynamic crosstalk for different MIS- and MES-based TSV shapes. A significant improvement in the cross-coupling behavior can be obtained using the MES-based tapered TSV compared to the other MIS structures. Additionally, the power delay product (PDP) of the tapered MES is reduced by 92.4% compared to the conventional MIS-based cylindrical TSV.

scholarly journals Investigating Parallel Programming Paradigms in HeMPS MPSoC Platform

2019 ◽  
Author(s):  
Geaninne Lopes ◽  
Aline Mello ◽  
Ewerson Carvalho ◽  
César Marcon
Keyword(s):  
Parallel Programming ◽  
Power Dissipation ◽  
Execution Time ◽  
Matrix Multiplication ◽  
Divide And Conquer ◽  
Image Manipulation ◽  
Multiprocessor System ◽  
Input Size ◽  
Programming Paradigms ◽  
The Impact

This work investigates the use of parallel programming paradigms in the development of applications targeting a Multiprocessor System-on-Chip (MPSoC). We implemented Matrix Multiplication, Image Manipulation and Advanced Encryption Standard (AES) applications in the Master-Slave, Pipeline and Divide-and-Conquer paradigms, and applied execution time and power dissipation as criteria for evaluating the performance of the applications executing according to the paradigms on an MPSoC architecture. The obtained results allowed ​us to conclude that there are optimal application-paradigm relations. Pipeline presents lower execution time and lower power dissipation for the Image Manipulation application; whereas, Master-Slave performs better for the Matrix Multiplication and AES applications. However, when the input size of the applications increases, the Divide-and-Conquer paradigm tends to minimize the execution time for Matrix Multiplication application. ​The main contributions of this work are the development of applications, considering different paradigms, and the impact evaluation of these paradigms on MPSoC architecture.

System Level Thermal Optimization of an Automotive Lightning Module Incorporating Several Power Devices

2007 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Performance ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
System Level ◽  
Total Power ◽  
Main Concern ◽  
Optimized Design ◽  
Passive Components ◽  
Thermal Budget ◽  
The Impact

The conjugate thermal performance of microelectronics module incorporating several power packages and additional passive components in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The automotive industry deals on a daily basis with multiple packaging and module-level thermal issues when reducing the size of components for a lightning system in a car, while managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance of the lightning system. The main concern is related to the possibility of exceeding the thermal budget for a large system incorporating several PQFN (Power Quad Flat No-Lead Package) packages with additional heat dissipation devices in an enclosure, at an external ambient temperature of 85°C. Due to the compactness of the device, there are only limited solutions to extract the heat from the high power dissipation system. The impact on the thermal balance of the trace dissipation, the location and size of the pins connecting the two boards (motherboard and daughter board) forming the system, the header heating and other passive components under various powered conditions are evaluated. A revised model includes additional pins (reduced diameter), modified motherboard and harness structures and their locations; the impact of additional heater traces on both top and bottom surfaces of the motherboard, and a modified daughter board design, is also evaluated. The resulting peak temperatures range from 118.3°C to 137.3°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.4°C/W to 8.8°C/W. Rja is defined as the temperature difference between the peak device and ambient divided by the total power dissipation of the PQFN packages. An optimized design is further evaluated, with lowered thermal resistance from the motherboard, the board-to-board pins, the junction box board, and the wiring harness. The thermal budget is satisfied, as the peak temperatures reached by the two designs are below the 150°C limit. Additional experimental results are used to benchmark the simulation results, within 1–6% accuracy.

scholarly journals Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/VddLibrary and Device Sizing

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Yibo Chen ◽  
Yu Wang ◽  
Yuan Xie ◽  
Andres Takach
Keyword(s):  
Power Dissipation ◽  
Process Variations ◽  
Behavioral Synthesis ◽  
Parametric Yield ◽  
Power Yield ◽  
Resource Binding ◽  
Resource Library ◽  
And Performance ◽  
High Level ◽  
The Impact

The ever-increasing chip power dissipation in SoCs has imposed great challenges on today’s circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vddoptimizations are performed under deterministic conditions. With the increasing process variability that has significant impact on both the power dissipation and performance of circuit designs, it is necessary to employ statistical approaches in analysis and optimizations for low power. This paper studies the impact of process variations on the multi-Vth/Vddtechnique at the behavioral synthesis level. A multi-Vth/Vddresource library is characterized for delay and power variations at different voltage combinations. Meanwhile, device sizing is performed on the resources in the library to mitigate the impact of variation, and to enlarge the design space for better quality of the design choice. A parametric yield-driven resource binding algorithm is then proposed, which uses the characterized power and delay distributions and efficiently maximizes power yield under a timing yield constraint. During the resource binding process, voltage level converters are inserted between resources when required. Experimental results show that significant power reduction can be achieved with the proposed variation-aware framework, compared with traditional worstcase based deterministic approaches.

scholarly journals TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

2019 ◽  
Vol 8 (2S2) ◽  
pp. 226-229
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Power Supply Voltage ◽  
Large Power ◽  
Flash Adc ◽  
Analog To Digital ◽  
Tiq Comparator ◽  
The Impact

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

scholarly journals Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1930
Author(s):  
Azwad Tamir ◽  
Milad Salem ◽  
Jie Lin ◽  
Qutaiba Alasad ◽  
Jiann-shiun Yuan
Keyword(s):  
Power Dissipation ◽  
Total Power ◽  
3D Design ◽  
3D Ic ◽  
3D Ics ◽  
Custom Made ◽  
Partitioning Algorithms ◽  
Automation Tools ◽  
The Impact ◽  
Place And Route

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

A Novel Low Power Technique for FinFET Domino OR Logic

2020 ◽  
pp. 2150117
Author(s):  
Kajal ◽  
Vijay Kumar Sharma
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Logic Gates ◽  
Leakage Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Large Power ◽  
Leakage Reduction ◽  
The Impact

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

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