scholarly journals Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1930
Author(s):  
Azwad Tamir ◽  
Milad Salem ◽  
Jie Lin ◽  
Qutaiba Alasad ◽  
Jiann-shiun Yuan
Keyword(s):  
Power Dissipation ◽  
Total Power ◽  
3D Design ◽  
3D Ic ◽  
3D Ics ◽  
Custom Made ◽  
Partitioning Algorithms ◽  
Automation Tools ◽  
The Impact ◽  
Place And Route

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method

2009 ◽  
Author(s):  
Je-Hyoung Park ◽  
Ali Shakouri ◽  
Sung-Mo Kang
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Three Dimensional ◽  
Computation Time ◽  
Maximum Error ◽  
3D Ic ◽  
Additional Advantage ◽  
3D Ics ◽  
Ic Technology ◽  
Power Blurring

CMOS VLSI technology has been facing various technical challenges as the feature sizes scale down. To overcome the challenges imposed by the shrink of the conventional on-chip interconnect system in IC chips, alternative interconnect technologies are being developed: one of them is three dimensional chips (3D ICs). Even though 3D IC technology is a promising solution for interconnect bottlenecks, thermal issues can be exacerbated. Thermal-aware design and optimization will be more critical in 3D IC technology than conventional planar IC technology, and hence accurate temperature profiles of each active layer will become very important. In 3D ICs, temperature profile of one layer depends not only on its own power dissipation but also on the heat transferred from other layers. Thus, thermal considerations for 3D ICs need to be done in a holistic manner even if each layer can be designed and fabricated individually. Conventional grid-based temperature computation methods are accurate but are computationally expensive, especially for 3D ICs. To increase computational efficiency, we developed a matrix convolution technique, called Power Blurring (PB) for 3D ICs. The temperature resulting from any arbitrary power dissipation in each layer of the 3D chip can be computed quickly. The PB method has been validated against commercial FEA software, ANSYS. Our method yields good results with maximum error less than 2% for various case studies and reduces the computation time by a factor of ∼ 60. The additional advantage is the possibility to evaluate different power dissipation profiles without the need to re-mesh the whole 3D chip structure.

System Level Thermal Optimization of an Automotive Lightning Module Incorporating Several Power Devices

2007 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Performance ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
System Level ◽  
Total Power ◽  
Main Concern ◽  
Optimized Design ◽  
Passive Components ◽  
Thermal Budget ◽  
The Impact

The conjugate thermal performance of microelectronics module incorporating several power packages and additional passive components in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The automotive industry deals on a daily basis with multiple packaging and module-level thermal issues when reducing the size of components for a lightning system in a car, while managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance of the lightning system. The main concern is related to the possibility of exceeding the thermal budget for a large system incorporating several PQFN (Power Quad Flat No-Lead Package) packages with additional heat dissipation devices in an enclosure, at an external ambient temperature of 85°C. Due to the compactness of the device, there are only limited solutions to extract the heat from the high power dissipation system. The impact on the thermal balance of the trace dissipation, the location and size of the pins connecting the two boards (motherboard and daughter board) forming the system, the header heating and other passive components under various powered conditions are evaluated. A revised model includes additional pins (reduced diameter), modified motherboard and harness structures and their locations; the impact of additional heater traces on both top and bottom surfaces of the motherboard, and a modified daughter board design, is also evaluated. The resulting peak temperatures range from 118.3°C to 137.3°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.4°C/W to 8.8°C/W. Rja is defined as the temperature difference between the peak device and ambient divided by the total power dissipation of the PQFN packages. An optimized design is further evaluated, with lowered thermal resistance from the motherboard, the board-to-board pins, the junction box board, and the wiring harness. The thermal budget is satisfied, as the peak temperatures reached by the two designs are below the 150°C limit. Additional experimental results are used to benchmark the simulation results, within 1–6% accuracy.

Design of spline surface vacuum gripper for pick and place robotic arms

2020 ◽  
Vol 4 (2) ◽  
pp. 48-55
Author(s):  
A. S. Jamaludin ◽  
M. N. M. Razali ◽  
N. Jasman ◽  
A. N. A. Ghafar ◽  
M. A. Hadi
Keyword(s):  
Cycle Time ◽  
Industrial Robot ◽  
Annealing Process ◽  
Vacuum Suction ◽  
Robotic Arms ◽  
Custom Made ◽  
Pick And Place ◽  
Manufacturing Procedure ◽  
Production Flexibility ◽  
The Impact

The gripper is the most important part in an industrial robot. It is related with the environment around the robot. Today, the industrial robot grippers have to be tuned and custom made for each application by engineers, by searching to get the desired repeatability and behaviour. Vacuum suction is one of the grippers in Watch Case Press Production (WCPP) and a mechanism to improve the efficiency of the manufacturing procedure. Pick and place are the important process for the annealing process. Thus, by implementing vacuum suction gripper, the process of pick and place can be improved. The purpose of vacuum gripper other than design vacuum suction mechanism is to compare the effectiveness of vacuum suction gripper with the conventional pick and place gripper. Vacuum suction gripper is a mechanism to transport part and which later sequencing, eliminating and reducing the activities required to complete the process. Throughout this study, the process pick and place became more effective, the impact on the production of annealing process is faster. The vacuum suction gripper can pick all part at the production which will lower the loss of the productivity. In conclusion, vacuum suction gripper reduces the cycle time about 20%. Vacuum suction gripper can help lower the cycle time of a machine and allow more frequent process in order to increase the production flexibility.

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Heechun Park ◽  
Bon Woong Ku ◽  
Kyungwook Chang ◽  
Da Eun Shim ◽  
Sung Kyu Lim
Keyword(s):  
State Of The Art ◽  
Physical Design ◽  
Design Flow ◽  
Design Tools ◽  
Mixed Design ◽  
Power Performance ◽  
3D Design ◽  
Qualitative And Quantitative ◽  
3D Ics ◽  
Power Delay Product

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

Electrical-Thermal-Reliability Co-Design for TSV-Based 3D-ICs

2015 ◽  
Author(s):  
Tiantao Lu ◽  
Ankur Srivastava
Keyword(s):  
Mechanical Stress ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Thermal Reliability ◽  
Conduction Path ◽  
Placement Problem ◽  
Thermal Profile ◽  
3D Ic ◽  
3D Ics ◽  
Simulation Based

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.

scholarly journals A 0.6-V to 1-V Audio ΔΣ Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
Liyuan Liu ◽  
Dongmei Li ◽  
Zhihua Wang
Keyword(s):  
Power Dissipation ◽  
Total Power ◽  
Third Order ◽  
Power Cost ◽  
Threshold Voltages ◽  
Nonlinear Amplifier ◽  
Amplifier Gain ◽  
Low Threshold ◽  
Single Comparator ◽  
Circuit Techniques

This paper presents a discrete time, single loop, third order ΔΣ modulator. The input feed forward technique combined with 5-bit quantizer is adopted to suppress swings of integrators. Harmonic distortions as well as the noise mixture due to the nonlinear amplifier gain are prevented. The design of amplifiers is hence relaxed. To reduce the area and power cost of the 5-bit quantizer, the successive approximation quantizer with only a single comparator instead of traditional flash quantizer is employed. Fabricated in 65 nm CMOS, the modulator achieves 95 dB peak SNDR at 1-V supply with 24 kHz. Thanks to low swing circuit techniques and low threshold voltages of devices, the peak SNDR maintains 90.2 dB under 0.6-V low supply. The total power dissipation is 371 μW at 1-V and drops to only 133 μW at 0.6-V.

Abstract P315: Increase in Stress May Contribute to Lower Heart Rate Variability in Healthy Young Subjects

Circulation ◽  
2012 ◽  
Vol 125 (suppl_10) ◽  
Author(s):  
Amanda C Costa ◽  
Ana Gabriela C Silva ◽  
Cibele T Ribeiro ◽  
Guilherme A Fregonezi ◽  
Fernando A Dias
Keyword(s):  
Cardiovascular Disease ◽  
Heart Rate ◽  
Heart Rate Variability ◽  
Healthy Volunteers ◽  
Perceived Stress ◽  
Low Frequency ◽  
Statistical Correlation ◽  
Total Power ◽  
The Impact ◽  
Nonparametric Correlation

Background: Stress is one of the risk factors for cardiovascular disease and decreased heart rate variability is associated to increased mortality in some cardiac diseases. The aim of the study was to assess the impact of perceived stress on cardiac autonomic regulation in young healthy volunteers. Methods: 35 young healthy volunteers (19 to 29 years old, 6 men) from a Brazilian population were assessed for perceived stress by the translated and validated Perceived Stress Scale (PSS, 14 questions) and had the R-R intervals recorded at rest on supine position (POLAR RS800CX) and analyzed (5 minutes, Kubius HRV software) by Fast-Fourier Transform for quantification of Heart Rate Variability (HRV). Results: Average data (±SD) for age, heart rate, BMI, waist circumference and percentage of body fat (%BF) were: 21.3±2.7 years; 65.5±7.9 bpm; 22.3±1.9 Kg/m 2 ; 76.0±6.1 cm and 32.1±6.6%; respectively. The mean score for the PSS-14 was 23.5±7.2 and for the HRV parameter as follow: SSDN=54.8±21.2ms; rMSSD=55.9±32.2ms; low-frequency (LF)= 794.8±579.7ms 2 ; High-frequency (HF)= 1508.0±1783.0 ms 2 ; LF(n.u.)= 41.1±16.2; HF(n.u.)= 58.9±16.2; LF/HF=0.89±0.80 and Total power (TP)= 3151±2570ms 2 . Spearman nonparametric correlation was calculated and there was a significant correlation of PSS-14 scores and LF (ms 2 ) (r=−0.343; p= 0.044). Other HRV variables did not shown significant correlation but also had negative values for Spearman r (TP r=−0.265, p=0.124; HF r=−0.158; SSDN r=−0.207; rMSSD r=−0.243, p=0.160). LF/HF and LF(n.u.) did not correlate to PSS-14 having Spearman r very close to zero (LF/HF r=−0.007, p=0.969; LF(n.u.) r=−0.005, p=0.976). No correlation was found for HRV parameters and BMI and there was a trend for statistical correlation of %BF and LF (ms 2 ) (r=−0.309, p=0.071). Conclusions: These data demonstrate a possible association of perceived stress level and HRV at rest. Changes in LF can be a consequence of both sympathetic and parasympathetic activity, however, analyzing the other variables HF, TP, SSDN and rMSSD (all negative Spearman r) and due to the lack of changes in LF/HF ratio and LF(n.u.) we interpret that increased stress may be associated to decrease in overall heart rate variability. These changes were seen in healthy individuals and may point out an important mechanism in cardiovascular disease development.

Direct Outer Ring Cooling of a High Speed Jet Engine Mainshaft Ball Bearing: Experimental Investigation Results

2010 ◽  
Author(s):  
Peter Gloeckner ◽  
Klaus Dullenkopf ◽  
Michael Flouros
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Ball Bearing ◽  
Operating Conditions ◽  
Outer Ring ◽  
Outer Diameter ◽  
Propulsion Systems ◽  
Jet Engine ◽  
Power Loss Reduction ◽  
The Impact

Operating conditions in high speed mainshaft ball bearings applied in new aircraft propulsion systems require enhanced bearing designs and materials. Rotational speeds, loads, demands on higher thrust capability, and reliability have increased continuously over the last years. A consequence of these increasing operating conditions are increased bearing temperatures. A state of the art jet engine high speed ball bearing has been modified with an oil channel in the outer diameter of the bearing. This oil channel provides direct cooling of the outer ring. Rig testing under typical flight conditions has been performed to investigate the cooling efficiency of the outer ring oil channel. In this paper the experimental results including bearing temperature distribution, power dissipation, bearing oil pumping and the impact on oil mass and parasitic power loss reduction are presented.

scholarly journals ZTC bias point of advanced fin based device: The importance and exploration

2015 ◽  
Vol 28 (3) ◽  
pp. 393-405 ◽  
Author(s):  
Sushanta Mohapatra ◽  
Kumar Pradhan ◽  
Prasanna Sahu
Keyword(s):  
Power Dissipation ◽  
Temperature Compensation ◽  
Performance Metrics ◽  
Zero Temperature ◽  
Sweet Spot ◽  
Static Power ◽  
20 Nm ◽  
Bias Point ◽  
The Impact ◽  
Present Understanding

The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.

scholarly journals Transfiguring Healthcare: Three-Dimensional Printing in Pharmaceutical Sciences; Trends during COVID-19: A Review

2021 ◽  
pp. 207-218
Author(s):  
K. G. Siree ◽  
T. M. Amulya ◽  
T. M. Pramod Kumar ◽  
S. Sowmya ◽  
K. Divith ◽  
...  
Keyword(s):  
3D Printing ◽  
Medical Devices ◽  
Three Dimensional ◽  
Pharmaceutical Sciences ◽  
Three Dimensional Printing ◽  
Custom Made ◽  
High Degree ◽  
The Impact ◽  
Dimensional Printing ◽  
Shed Light

Three-dimensional (3D) printing is a unique technique that allows for a high degree of customisation in pharmacy, dentistry and in designing of medical devices. 3D printing satiates the increasing exigency for consumer personalisation in these fields as custom-made medicines catering to the patients’ requirements are novel advancements in drug therapy. Current research in 3D printing indicates towards reproducing an organ in the form of a chip; paving the way for more studies and opportunities to perfecting the existing technique. In addition, we will also attempt to shed light on the impact of 3D printing in the COVID-19 pandemic.

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