Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch With Temperature-Compensated Fast Turn-on Technique for Achieving Switching Frequency of 50 MHz and Slew Rate of 118.3 V/Ns

Author(s):  
Yu-Yung Kao ◽  
Sheng-Hsi Hung ◽  
Hsuan-Yu Chen ◽  
Jia-Jyun Lee ◽  
Ke-Horng Chen ◽  
...  
Energies ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2449
Author(s):  
Hongyan Zhao ◽  
Jiangui Chen ◽  
Yan Li ◽  
Fei Lin

Compared with a silicon MOSFET device, the SiC MOSFET has many benefits, such as higher breakdown voltage, faster action speed and better thermal conductivity. These advantages enable the SiC MOSFET to operate at higher switching frequencies, while, as the switching frequency increases, the turn-on loss accounts for most of the loss. This characteristic severely limits the applications of the SiC MOSFET at higher switching frequencies. Accordingly, an SRD-type drive circuit for a SiC MOSFET is proposed in this paper. The proposed SRD-type drive circuit can suppress the turn-on oscillation of a non-Kelvin packaged SiC MOSFET to ensure that the SiC MOSFET can work at a faster turn-on speed with a lower turn-on loss. In this paper, the basic principle of the proposed SRD-type drive circuit is analyzed, and a double pulse platform is established. For the purpose of proof-testing the performance of the presented SRD-type drive circuit, comparisons and experimental verifications between the traditional gate driver and the proposed SRD-type drive circuit were conducted. Our experimental results finally demonstrate the feasibility and effectiveness of the proposed SRD-type drive circuit.


2021 ◽  
Vol 11 (5) ◽  
pp. 2210
Author(s):  
Bartosz Lasek ◽  
Przemysław Trochimiuk ◽  
Rafał Kopacz ◽  
Jacek Rąbkowski

This article discusses an active gate driver for a 1.7 kV/325 A SiC MOSFET module. The main purpose of the driver is to adjust the gate voltage in specified moments to speed up the turn-on cycle and reduce the amount of dissipated energy. Moreover, an adequate manipulation of the gate voltage is necessary as the gate current should be reduced during the rise of the drain current to avoid overshoots and oscillations. The gate voltage is switched at the right moments on the basis of the feedback signal provided from a measurement of the voltage across the parasitic source inductance of the module. This approach simplifies the circuit and provides no additional power losses in the measuring circuit. The paper contains the theoretical background and detailed description of the active gate driver design. The model of the parasitic-based active gate driver was verified using the double-pulse procedure both in Saber simulations and laboratory experiments. The active gate driver decreases the turn-on energy of a 1.7 kV/325 A SiC MOSFET by 7% comparing to a conventional gate driver (VDS = 900 V, ID = 270 A, RG = 20 Ω). Furthermore, the proposed active gate driver lowered the turn-on cycle time from 478 to 390 ns without any serious oscillations in the main circuit.


2011 ◽  
Vol 679-680 ◽  
pp. 649-652 ◽  
Author(s):  
Jang Kwon Lim ◽  
Georg Tolstoy ◽  
Dimosthenis Peftitsis ◽  
Jacek Rabkowski ◽  
Mietek Bakowski ◽  
...  

The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5•104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.


2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000152-000158
Author(s):  
J. Valle Mayorga ◽  
C. Gutshall ◽  
K. Phan ◽  
I. Escorcia ◽  
H. A. Mantooth ◽  
...  

SiC power semiconductors have the capability of greatly outperforming Si-based power devices. Faster switching and smaller on-state losses coupled with higher voltage blocking and temperature capabilities, make SiC a very attractive semiconductor for high performance, high power density power modules. However, the temperature capabilities and increased power density are fully utilized only when the gate driver is placed next to the SiC devices. This requires the gate driver to successfully operate under these extreme conditions with reduced or no heat sinking requirements, allowing the full realization of a high efficiency, high power density SiC power module. In addition, since SiC devices are usually connected in a half or full bridge configuration, the gate driver should provide electrical isolation between the high and low voltage sections of the driver itself. This paper presents a 225 degrees Celsius operable, Silicon-On-Insulator (SOI) high voltage isolated gate driver IC for SiC devices. The IC was designed and fabricated in a 1 μm, partially depleted, CMOS process. The presented gate driver consists of a primary and a secondary side which are electrically isolated by the use of a transformer. The gate driver IC has been tested at a switching frequency of 200 kHz at 225 degrees Celsius while exhibiting a dv/dt noise immunity of at least 45 kV/μs.


2020 ◽  
Vol 13 (9) ◽  
pp. 1797-1806 ◽  
Author(s):  
Pavan Singh Tomar ◽  
N Sandeep ◽  
Arun Kumar Verma ◽  
Manaswi Srivastava

Author(s):  
Toni Prasetya ◽  
F. Danang Wijaya ◽  
Eka Firmansyah

Enhancing the switching frequency can increase the power density of a fullbridge dc-dc converter. However, power loss in switches will increase due to the intersection of voltage and current during turn-on and turn-off transition process. The switching power loss can be reduced by making the condition of zero voltage switching (ZVS) which in this study is obtained by using the phase-shifted PWM method. Achieving this condition requires appropriate parameters such as deadtime, leakage inductance, and the primary current of transformer in sufficient value. In this study, ZVS is achieved when the transformer leakage inductance of 14.12 μH is added with external inductance of 24.29 μH which is installed in series with transformer and when the primary current of transformer is more than 1.289 A.


Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1540
Author(s):  
Longkun Lai ◽  
Ronghua Zhang ◽  
Kui Cheng ◽  
Zhiying Xia ◽  
Chun Wei ◽  
...  

Integration is a key way to improve the switching frequency and power density for a DC-DC converter. A monolithic integrated GaN based DC-DC buck converter is realized by using a gate driver and a half-bridge power stage. The gate driver is composed of three stages (amplitude amplifier stage, level shifting stage and resistive-load amplifier stage) to amplify and modulate the driver control signal, i.e., CML (current mode logic) level of which the swing is from 1.1 to 1.8 V meaning that there is no need for an additional buffer or preamplifier for the control signal. The gate driver can provide sufficient driving capability for the power stage and improve the power density efficiently. The proposed GaN based DC-DC buck converter is implemented in the 0.25 μm depletion mode GaN-on-SiC process with a chip area of 1.7 mm × 1.3 mm, which is capable of operating at high switching frequency up to 200 MHz and possesses high power density up to 1 W/mm2 at 15 V output voltage. To the authors’ knowledge, this is the highest power density for GaN based DC-DC converter at the hundreds of megahertz range.


2019 ◽  
Author(s):  
Boris Curuvua ◽  
Lihua Chen ◽  
Fan Xu
Keyword(s):  
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