Fabrication of the Flexible Sensor Using SOI Wafer by Removing the Thick Silicon Layer

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

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High-resolution transmission electron microscopic study of highly oxygen doped silicon layer

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100155438 ◽

1989 ◽

Vol 47 ◽

pp. 692-693

Author(s):

H. Takaoka ◽

M. Tomita ◽

T. Hayashi

Keyword(s):

High Resolution ◽

Oxygen Concentration ◽

Silicon Layer ◽

Detailed Structure ◽

Electron Microscopic ◽

Cross Sectional ◽

Transmission Electron ◽

Doped Silicon ◽

Argon Ion

High resolution transmission electron microscopy (HRTEM) is the effective technique for characterization of detailed structure of semiconductor materials. Oxygen is one of the important impurities in semiconductors. Detailed structure of highly oxygen doped silicon has not clearly investigated yet. This report describes detailed structure of highly oxygen doped silicon observed by HRTEM. Both samples prepared by Molecular beam epitaxy (MBE) and ion implantation were observed to investigate effects of oxygen concentration and doping methods to the crystal structure.The observed oxygen doped samples were prepared by MBE method in oxygen environment on (111) substrates. Oxygen concentration was about 1021 atoms/cm3. Another sample was silicon of (100) orientation implanted with oxygen ions at an energy of 180 keV. Oxygen concentration of this sample was about 1020 atoms/cm3 Cross-sectional specimens of (011) orientation were prepared by argon ion thinning and were observed by TEM at an accelerating voltage of 400 kV.

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Behavior of contact-silicided TFSOI gate structures

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100172036 ◽

1994 ◽

Vol 52 ◽

pp. 860-861

Author(s):

N. David Theodore ◽

Juergen Foerstner ◽

Peter Fejes

Keyword(s):

Semiconductor Device ◽

Series Resistance ◽

Field Effect Transistors ◽

Silicon Layer ◽

Device Fabrication ◽

Silicon On Insulator ◽

Continuous Layer ◽

Buried Oxide ◽

Device Structures ◽

Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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Electron beam induced current study of thin silicon layers on insulator substrate

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100176228 ◽

1990 ◽

Vol 48 (4) ◽

pp. 618-619

Author(s):

A. Buczkowski ◽

Z. J. Radzimski ◽

J. C. Russ ◽

G. A. Rozgonyi

Keyword(s):

Electron Beam ◽

Energy Loss ◽

Beam Energy ◽

Collection Efficiency ◽

Silicon Layer ◽

Depletion Layer ◽

Incident Electron Energy ◽

Induced Current ◽

Electron Hole ◽

Electron Beam Induced Current

If a thickness of a semiconductor is smaller than the penetration depth of the electron beam, e.g. in silicon on insulator (SOI) structures, only a small portion of incident electrons energy , which is lost in a superficial silicon layer separated by the oxide from the substrate, contributes to the electron beam induced current (EBIC). Because the energy loss distribution of primary beam is not uniform and varies with beam energy, it is not straightforward to predict the optimum conditions for using this technique. Moreover, the energy losses in an ohmic or Schottky contact complicate this prediction. None of the existing theories, which are based on an assumption of a point-like region of electron beam generation, can be used satisfactorily on SOI structures. We have used a Monte Carlo technique which provide a simulation of the electron beam interactions with thin multilayer structures. The EBIC current was calculated using a simple one dimensional geometry, i.e. depletion layer separating electron- hole pairs spreads out to infinity in x- and y-direction. A point-type generation function with location being an actual location of an incident electron energy loss event has been assumed. A collection efficiency of electron-hole pairs was assumed to be 100% for carriers generated within the depletion layer, and inversely proportional to the exponential function of depth with the effective diffusion length as a parameter outside this layer. A series of simulations were performed for various thicknesses of superficial silicon layer. The geometries used for simulations were chosen to match the "real" samples used in the experimental part of this work. The theoretical data presented in Fig. 1 show how significandy the gain decreases with a decrease in superficial layer thickness in comparison with bulk material. Moreover, there is an optimum beam energy at which the gain reaches its maximum value for particular silicon thickness.

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Short Channel Poly-Si TFT with Single Grain Boundary by Excimer Laser Annealing on Al-masked a-Si Layer

MRS Proceedings ◽

10.1557/proc-715-a7.8 ◽

2002 ◽

Vol 715 ◽

Author(s):

Sang-Hoon Jung ◽

Jae-Hoon Lee ◽

Min-Koo Han

Keyword(s):

Grain Boundary ◽

Laser Annealing ◽

Thin Film Transistor ◽

High Mobility ◽

Silicon Layer ◽

Silicon Thin Film ◽

Short Channel ◽

Excimer Laser Annealing ◽

Boundary Density ◽

Single Grain

AbstractA short channel polycrystalline silicon thin film transistor (poly-Si TFT), which has single grain boundary in the center of channel, is reported. The reported poly-Si TFT employs lateral grain growth method through aluminum patterns, which acts as a selective beam mask and a lateral heat sink during the laser irradiation, on an amorphous silicon layer. The electrical characteristics of the proposed poly-Si TFT have been considerably improved due to grain boundary density lowered. The reported short channel poly-Si TFT with single grain boundary exhibits high mobility as 222 cm2/Vsec and large on/off current ratio exceeding 1 × 108.

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High Temperature n- and p-type Doped Microcrystalline Silicon Layers Grown by VHF PECVD Layer-by-Layer Deposition

MRS Proceedings ◽

10.1557/proc-762-a6.8 ◽

2003 ◽

Vol 762 ◽

Cited By ~ 7

Author(s):

A. Gordijn ◽

J.K. Rath ◽

R.E.I. Schropp

Keyword(s):

Activation Energy ◽

High Temperature ◽

High Temperatures ◽

Continuous Wave ◽

Hydrogen Plasma ◽

Silicon Layer ◽

Dark Conductivity ◽

High Deposition Rate ◽

Layer By Layer ◽

Microcrystalline Silicon

AbstractDue to the high temperatures used for high deposition rate microcrystalline (μc-Si:H) and polycrystalline silicon, there is a need for compact and temperature-stable doped layers. In this study we report on films grown by the layer-by-layer method (LbL) using VHF PECVD. Growth of an amorphous silicon layer is alternated by a hydrogen plasma treatment. In LbL, the surface reactions are separated time-wise from the nucleation in the bulk. We observed that it is possible to incorporate dopant atoms in the layer, without disturbing the nucleation. Even at high substrate temperatures (up to 400°C) doped layers can be made microcrystalline. At these temperatures, in the continuous wave case, crystallinity is hindered, which is generally attributed to the out-diffusion of hydrogen from the surface and the presence of impurities (dopants).We observe that the parameter window for the treatment time for p-layers is smaller compared to n-layers. Moreover we observe that for high temperatures, the nucleation of p-layers is more adversely affected than for n-layers. Thin, doped layers have been structurally, optically and electrically characterized. The best n-layer made at 400°C, with a thickness of only 31 nm, had an activation energy of 0.056 eV and a dark conductivity of 2.7 S/cm, while the best p-layer made at 350°C, with a thickness of 29 nm, had an activation energy of 0.11 V and a dark conductivity of 0.1 S/cm. The suitability of these high temperature n-layers has been demonstrated in an n-i-p microcrystalline silicon solar cell with an unoptimized μc-Si:H i-layer deposited at 250°C and without buffer. The Voc of the cell is 0.48 V and the fill factor is 70 %.

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