Analysis and Design of a Precise Voltage Buffer

2015 ◽  
Vol 24 (04) ◽  
pp. 1550058 ◽  
Author(s):  
Tohid Moradi Khaneshan ◽  
Mojde Nematzade ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei
Keyword(s):  
Power Supply ◽  
Volterra Series ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Open Loop ◽  
Analysis And Design ◽  
Source Follower ◽  
Unity Gain ◽  
Local Feedback ◽  
Poles And Zeros

An open loop voltage buffer with an exact unity gain using a positive local feedback technique with a conventional source follower is proposed. Stability of the buffer is determined by evaluating the location of the poles and zeros and its linearity is studied using Volterra series expansion. The proposed buffer is laid out in 0.35-μm standard CMOS technology. Post layout simulations demonstrate that the buffer gain is close to unity with less than 0.2% error. The power consumption is 10 mw from a 3.3 V power supply and the achieved total harmonic distortion is -78 dB for a 10 MHz input frequency. Also Monte-Carlo simulations are carried out to investigate effects of random mismatches on the circuit operation.

scholarly journals ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

2019 ◽  
Vol 8 (3) ◽  
Author(s):  
Arash Rezapour ◽  
Mohammad Bagher Tavakoli ◽  
Farbod Setoudeh
Keyword(s):  
Power Supply ◽  
Data Transfer ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Analysis And Design ◽  
Second Stage ◽  
Total Power Consumption

A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stage is not used the amplifier and instead the buffer is used for data transfer to the second stage. The speed of this converter is 350MS/s. An amplifier circuit with accurate gain of 6 and a very accurate unit gain buffer circuit that are open loop with a new structure were. used. In this Converter, the first 3 bits are extracted simultaneously with sampling. The proposed analog-to-digital converter was designed with the total power consumption 75mW using power supply of 1.8v.

A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

2007 ◽  
Vol 16 (04) ◽  
pp. 627-639 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
WEERACHAI NAKHLO
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Conveyor ◽  
Common Source ◽  
Output Stage ◽  
Circuit Performance ◽  
Rail To Rail ◽  
Source Follower ◽  
Transfer Error

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

High Frequency Unity Gain Buffer in 90-nm CMOS Technology

2016 ◽  
Vol 25 (07) ◽  
pp. 1650071
Author(s):  
Shuo Li ◽  
Xiaomeng Zhang ◽  
Saiyu Ren
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Common Source ◽  
Active Load ◽  
Cmos Design ◽  
Saturation Region ◽  
Unity Gain ◽  
Unity Gain Buffer ◽  
Voltage Swing

A new unity gain buffer architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) buffer with source feedback offers improved performance compared to previously published source follower and source-coupled differential-pair-based unity gain buffers. A 90-nm CMOS design ([Formula: see text] equals 1.2[Formula: see text]V) of the buffer has the following performance parameters. With [Formula: see text]/[Formula: see text] of 10 fF/250 fF, [Formula: see text] is 4.4[Formula: see text]GHz, low frequency gain is 0.16[Formula: see text]dB, maximum input range within 2% gain variation is 260[Formula: see text]mV, total harmonic distortion (THD) is [Formula: see text]63.3[Formula: see text]dB, offset error (input offset minus output offset) is 26[Formula: see text]mV, and 1.06[Formula: see text]mW power consumption. The active load, low gain amplifiers eliminate stability issues and any need for compensation capacitors. The architecture facilitates a relatively large input/output voltage swing while keeping transistors operating in the saturation region, making it suitable for submicron technologies with low rail voltages.

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

2021 ◽  
pp. 2250056
Author(s):  
Urvashi Bansal ◽  
Abhilasha Bakre ◽  
Prem Kumar ◽  
Devansh Yadav ◽  
Mohit Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Slew Rate ◽  
Two Stage ◽  
Adaptive Biasing ◽  
Unity Gain ◽  
High Bandwidth ◽  
Cmos Amplifier

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

scholarly journals Performance of Source Follower Buffers Implemented with Standard and Strained Triple-Gate nFinFETs

2010 ◽  
Vol 5 (2) ◽  
pp. 168-173
Author(s):  
Marcelo Antonio Pavanello ◽  
João Antonio Martino ◽  
Eddy Simoen ◽  
Rita Rooyackers ◽  
Nadine Collaert ◽  
...  
Keyword(s):  
Harmonic Distortion ◽  
Channel Length ◽  
The Other ◽  
Double Gate ◽  
Voltage Gain ◽  
Source Follower ◽  
Unity Gain ◽  
Better Than ◽  
Strained Material ◽  
Output Conductance

In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

2016 ◽  
Vol 25 (08) ◽  
pp. 1650084 ◽  
Author(s):  
Liang Zhang ◽  
Dengquan Li ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Common Source ◽  
Digital Converter ◽  
Input Buffer ◽  
Analog To Digital ◽  
Source Follower ◽  
Time Interleaved

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

scholarly journals A Tunable-Gain Transimpedance Amplifier for CMOS-MEMS Resonators Characterization

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 82
Author(s):  
Rafel Perelló-Roig ◽  
Jaume Verd ◽  
Sebastià Bota ◽  
Jaume Segura
Keyword(s):  
Cmos Technology ◽  
Open Loop ◽  
Transimpedance Amplifier ◽  
Mems Devices ◽  
Monolithically Integrated ◽  
Mems Resonators ◽  
Electromechanical Performance ◽  
Cmos Mems ◽  
Promising Solution ◽  
On Chip

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This paper presents a transimpedance amplifier (TIA) fabricated using a commercial 0.35-µm CMOS technology specifically oriented to drive and sense monolithically integrated CMOS-MEMS resonators up to 50 MHz with a tunable transimpedance gain ranging from 112 dB to 121 dB. The output voltage noise is as low as 225 nV/Hz1/2—input-referred current noise of 192 fA/Hz1/2—at 10 MHz, and the power consumption is kept below 1-mW. In addition, the TIA amplifier exhibits an open-loop gain independent of the parasitic input capacitance—mostly associated with the MEMS layout—representing an advantage in MEMS testing compared to other alternatives such as Pierce oscillator schemes. The work presented includes the characterization of three types of MEMS resonators that have been fabricated and experimentally characterized both in open-loop and self-sustained configurations using the integrated TIA amplifier. The experimental characterization includes an accurate extraction of the electromechanical parameters for the three fabricated structures that enables an accurate MEMS-CMOS circuitry co-design.

Low Distortion Analog Front-End for Digital Electret Microphone

2013 ◽  
Vol 475-476 ◽  
pp. 1633-1637
Author(s):  
Seung Yong Bae ◽  
Jong Do Lee ◽  
Eun Ju Choe ◽  
Gil Cho Ahn
Keyword(s):  
Audio Signal ◽  
Cmos Technology ◽  
Common Mode ◽  
Electret Microphone ◽  
Front End ◽  
Voltage Variation ◽  
Analog Front End ◽  
Source Follower ◽  
Source Voltage ◽  
Low Distortion

This paper presents a low distortion analog front-end (AFE) circuit to process electret microphone output signal. A source follower is employed for the input buffer to interface electret microphone directly to the IC with level shifting. A single-ended to differential converter with output common-mode control is presented to compensate the common-mode variation resulted from gate to source voltage variation in the source follower. A replica stage is adopted to control the output bias voltage of the single-ended to differential converter. The prototype AFE circuit fabricated in a 0.35μm CMOS technology achieves 68.2dB peak SNDR and 79.9dB SFDR over an audio signal bandwidth of 20kHz with 2.5V supply while consuming 1.05mW.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

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