COMPLEMENTARY AND DOUBLE-EDGE BASED: A 5-BIT CMOS DIGITAL PULSE-WIDTH MODULATION (PWM) DESIGN WITH MULTIPLE OUTPUTS FOR LED DIMMING APPLICATION

2014 ◽  
Vol 23 (02) ◽  
pp. 1450030 ◽  
Author(s):  
YU-CHERNG HUNG
Keyword(s):  
Pulse Width ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Supply Voltage ◽  
Light Emitting Diode ◽  
Cmos Technology ◽  
Chip Area ◽  
Double Edge ◽  
Digital Pulse ◽  
Dimming Control

In this paper, a compact high-precision digital pulse-width modulation (DPWM) CMOS circuit is proposed. The circuit, with multiple output capability, allows brightness control of red, green, and blue (RGB) light emitting diode (LED) lighting. The PWM technique is used for LED dimming control to avoid the problem of color shifting. In this design, complementary concepts and hardware sharing are utilized to achieve a compact architecture and small chip area. A double-edge triggered technique is adopted to enhance the capability of high-speed operation. An experimental chip has been realized by using TSMC 0.18-μm CMOS technology. Simulation results show that the proposed 5-bit PWM circuit can operate at 200 MHz, 32 duty cycles adjustable, and within only 1-ns time error. The chip's measured results show that the new PWM circuit with three output channels works successfully at a supply voltage of 1.8-V, clock of 50-MHz, and resolution of 32 adjustable per channel. The core area of the chip is only 280 × 52.5 μm2.

scholarly journals Current mode pulse width modulation/pulse position modulation based on phase lock loop

2017 ◽  
Vol 68 (3) ◽  
pp. 180-187
Author(s):  
Pichet Wisartpong ◽  
Vorapong Silaphan ◽  
Sunee Kurutach ◽  
Paramote Wardkein
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Phase Lock Loop ◽  
Center Frequency ◽  
Loop Filter ◽  
Chip Area ◽  
Fully Integrated

Abstract In this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing amplifier circuit. It functions as PPM and PWM circuit is present. In addition, its frequency response is an analysis which electronic tuning BPF and LPF are obtained. The proposed circuit has been designed with 0.18 μm CMOS technology. The simulation results of this circuit can be operated at 2.5 V supply voltage, at center frequency 100 MHz. The linear range of input current can be adjusted from 43 μA to 109 μA, and the corresponding duty cycle of pulse width output is from 93% to 16% and the normalized pulse position is from 0.93 to 0.16. The power dissipation of this circuit is 4.68 mW with the total chip area is 28 μm × 60 μm.

scholarly journals The Design Methodology of Fully Digital Pulse Width Modulation

2021 ◽  
Vol 11 (4) ◽  
pp. 41
Author(s):  
Fadi R. Shahroury
Keyword(s):  
Pulse Width ◽  
Design Methodology ◽  
Pulse Width Modulation ◽  
Average Power ◽  
Cmos Technology ◽  
Good Choice ◽  
Ring Oscillator ◽  
Envelope Detector ◽  
Digital Pulse ◽  
Average Power Consumption

This paper describes the design methodology and calibration technique for a low-power digital pulse width modulation demodulator to enhance its robustness against the process, voltage, and temperature variations in different process corners, in addition to intra-die variability, which makes it a very good choice for implantable monitoring sensors. Furthermore, the core of the proposed demodulator is fully digital. Thus, along with the proposed design methodology, the proposed demodulator can be simply redesigned in advanced subnanometer CMOS technologies without much difficulty as compared to analog demodulators. The proposed demodulator consists of an envelope detector, a digitizer, a ring oscillator, and a data detector with digital calibration. All the proposed circuits are designed and simulated in the standard 1P9M TSMC’s 40 nm CMOS technology. Simulation results have shown that the circuit is capable of demodulating and recovering data from an input signal with a carrier frequency of 13.56 MHz and a data rate of 143 kB/s with an average power consumption of 5.62 μW.

A 0.5–1.2 V PWM CMOS DPS WITH 120 dB DYNAMIC RANGE FOR BIONIC HUMAN EYE IN DEEP SUBMICRON CMOS TECHNOLOGY

2014 ◽  
Vol 23 (02) ◽  
pp. 1450020 ◽  
Author(s):  
JIANGTAO XU ◽  
WEISONG JIN ◽  
KAIMING NIE ◽  
SUYING YAO
Keyword(s):  
High Speed ◽  
Pulse Width Modulation ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Digital Camera ◽  
Cmos Technology ◽  
Frame Rate ◽  
Clock Frequency ◽  
Human Eye ◽  
Digital Pixel

In this paper, a CMOS digital pixel sensor (DPS) with pixel-level ADC based on pulse width modulation (PWM) scheme is proposed to overcome the restriction of low supply voltage imposed by device scaling trend. The pixel operates with a dynamic current comparison scheme to avoid using complex in-pixel comparator and achieve a high dynamic range (DR). By adjusting clock frequency for different illumination, DR is further extended due to increasing the maximum detectable photocurrent and lowering the minimum detectable photocurrent. The pixel contains a photodiode (PD), an 11-bit in-pixel SRAM and other 11 transistors, and occupies an area of 7 μm × 7 μm, with a fill factor of 31.3% using a standard 65 nm CMOS technology. Simulation results show that this pixel can work at a supply voltage as low as 0.5 V with 120 dB DR and 80 dB linear DR (LDR). The properties of high DR and logarithmic response make the proposed digital pixel be capable of human eye. Frame rate achieves 246 fps with 640 × 480 pixel array by using in-pixel ADC and SRAM. This makes the digital pixel very suitable for high-speed snap shot digital camera application.

scholarly journals A low-noise current preamplifier in 120 nm CMOS technology

2008 ◽  
Vol 6 ◽  
pp. 213-217 ◽  
Author(s):  
H. Uhrmann ◽  
W. Gaberl ◽  
H. Zimmermann
Keyword(s):  
High Speed ◽  
Analog Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Special Focus ◽  
Current Mirror ◽  
Chip Area ◽  
The Impact

Abstract. In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS) based point-to-point data links or preamplifiers for photodetectors.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Dynamic vacuum pressure tracking control with high-speed on-off valves

2018 ◽  
Vol 232 (10) ◽  
pp. 1325-1336 ◽  
Author(s):  
Gang Yang ◽  
Kai Chen ◽  
Linglong Du ◽  
Jingmin Du ◽  
Baoren Li
Keyword(s):  
Mass Flow ◽  
Pulse Width ◽  
High Speed ◽  
Pulse Width Modulation ◽  
Sliding Mode ◽  
Tracking System ◽  
Vacuum Pressure ◽  
Chamber Pressure ◽  
Asymmetric Structure ◽  
The Impact

A vacuum pressure tracking system with high-speed on-off valves is a discontinuous system due to the discrete nature of high-speed on-off valves. Chamber pressure changes in the system are determined by the mass flow rates during the processes of charging and discharging. Here, a sliding mode controller with an asymmetric compensator based on average mass flow rate is designed for accurate vacuum pressure tracking. The controller output signal is converted into the duty cycles of the high-speed on-off valves via a pulse width modulation pulsing scheme. Owing to the extreme asymmetry of the processes, an asymmetric structure comprising one high-speed on-off valve in the charging unit and three high-speed on-off valves in the discharging unit is applied to weaken the impact of asymmetry. In addition, an asymmetric compensator is also designed to modify the pulse width modulation pulsing scheme to further eliminate the asymmetry. Experimental results indicate that the proposed controller achieves better performance in pressure tracking with the asymmetric compensator overcoming process asymmetry and enhancing system robustness.

scholarly journals Receiver Designs for Electronic Toll Collection Systems : A Survey

2020 ◽  
pp. 576-581
Author(s):  
Rarika Ravi ◽  
Anu Assis
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Power Level ◽  
Cmos Technology ◽  
Electronic Toll Collection ◽  
Chip Area ◽  
Advantages And Disadvantages ◽  
Digitally Controlled ◽  
Toll Collection

<p>This paper discusses about different receiver designs adopted so far for various electronic toll collection systems. A comparative analysis based on the discussions is also provided. It shows that each design has it's own advantages and disadvantages compared to others. The main aim of this paper is to identify the most suitable design. The researches shows that the receiver design described in the 5.8GHz digitally controlled DSRC receiver for Chinese electronic toll collection system is the most suitable one. Here all RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF-SoC. The proposed digitally controlled LNA and mixer circuits are elaborated. The technology used is 0.13μm CMOS technology. The RF block occupies a chip area of 0.75mm2. It consumes 22mA under a 1.5V supply voltage. The bit error rate maintains better than 10-6, the input power level varies from -75dBm to -8dBm. This design provides a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.</p>

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