scholarly journals Receiver Designs for Electronic Toll Collection Systems : A Survey

2020 ◽  
pp. 576-581
Author(s):  
Rarika Ravi ◽  
Anu Assis
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Power Level ◽  
Cmos Technology ◽  
Electronic Toll Collection ◽  
Chip Area ◽  
Advantages And Disadvantages ◽  
Digitally Controlled ◽  
Toll Collection

<p>This paper discusses about different receiver designs adopted so far for various electronic toll collection systems. A comparative analysis based on the discussions is also provided. It shows that each design has it's own advantages and disadvantages compared to others. The main aim of this paper is to identify the most suitable design. The researches shows that the receiver design described in the 5.8GHz digitally controlled DSRC receiver for Chinese electronic toll collection system is the most suitable one. Here all RF, IF blocks and digital baseband for on-chip automatic gain control, are integrated on an RF-SoC. The proposed digitally controlled LNA and mixer circuits are elaborated. The technology used is 0.13μm CMOS technology. The RF block occupies a chip area of 0.75mm2. It consumes 22mA under a 1.5V supply voltage. The bit error rate maintains better than 10-6, the input power level varies from -75dBm to -8dBm. This design provides a receiver sensitivity improvement of at least 25%, and a dynamic range enhancement of at least 12%.</p>

A CMOS Automatic Gain Control Circuit for Biomedical Applications

2015 ◽  
Vol 645-646 ◽  
pp. 1308-1313
Author(s):  
Zhi Qiang Gao ◽  
Fu Xiang Huang ◽  
Jing Li ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Exponential Function ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Cmos Technology ◽  
Chip Area ◽  
Gain Variation ◽  
Linearity Error

In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm2 of chip area.

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

scholarly journals Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 2931
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Grzegorz Blakiewicz
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Biomedical Sensors ◽  
Filter Synthesis ◽  
Cascade Method

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for buffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

scholarly journals A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2033
Author(s):  
Ahmed Elgreatly ◽  
Ahmed Dessouki ◽  
Hassan Mostafa ◽  
Rania Abdalla ◽  
El-sayed El-Rabaie
Keyword(s):  
Power Consumption ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Analog To Digital Converters ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

Area-Efficient Capacitor-Splitting Switching Scheme with a Nearly Constant Common-Mode Voltage for SAR ADCs

2019 ◽  
Vol 29 (10) ◽  
pp. 2020005
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Switching Scheme ◽  
Common Mode ◽  
Analog To Digital ◽  
Common Mode Voltage ◽  
Switching Method ◽  
Area Efficient

A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and [Formula: see text] (equal to [Formula: see text]/4) are combined together and optimized to realize the proposed switching scheme. [Formula: see text] is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology with a supply voltage of 0.6[Formula: see text]V and at a sampling rate of 20[Formula: see text]kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7[Formula: see text]dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42[Formula: see text]nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.

scholarly journals Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
Active Inductors ◽  
Low Pass ◽  
Optical Applications ◽  
Fifth Order

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals A Controllable Constant Power Generator in 0.35 μm CMOS Technology for Thermal-Based Sensor Applications

2018 ◽  
Vol 2018 ◽  
pp. 1-12
Author(s):  
Milena Zogović Erceg
Keyword(s):  
Relative Error ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Load Resistance ◽  
Cmos Technology ◽  
Constant Power ◽  
Power Generator ◽  
Sensor Applications ◽  
Wide Range ◽  
Resistive Loads

A CMOS controllable constant power generator based on multiplier/divider circuit is presented. It generates constant power for a wide range of the resistive loads. For the generated power of 5 mW, and the resistance range from 0.5 kΩ to 1.5 kΩ, the relative error of dissipated power is less than 0.6%. For single supply voltage of 5 V, presented controllable constant power generator generates power from 0.5 mW to 7.8 mW, for the load resistance dynamic range from 3 up to 15, while the relative error of generated power is less than 2%. The frequency bandwidth of the proposed design is up to 5 MHz. Through the detailed analysis of the loop gain, it is shown that the circuit has no stability problems.

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