Performance evaluation of novel low leakage Double-gate FinFET device at sub-22nm with LaAlO3 high-k gate oxide and TiN metal gate using quantum modeling

2014 ◽  
Author(s):  
Subha Subramaniam ◽  
Sangeeta M. Joshi ◽  
R. N. Awale
Keyword(s):  
Performance Evaluation ◽  
Gate Oxide ◽  
Double Gate ◽  
Metal Gate ◽  
Low Leakage ◽  
High K ◽  
Tin Metal ◽  
Quantum Modeling

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

Atomic Layer Deposition of Zirconium-Based High-k Metal Gate Oxide: Effect of Si Containing Zr Precursor

2015 ◽  
Vol 15 (1) ◽  
pp. 382-385
Author(s):  
Jun Hee Cho ◽  
Sang-Ick Lee ◽  
Jong Hyun Kim ◽  
Sang Jun Yim ◽  
Hyung Soo Shin ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Gate Oxide ◽  
Metal Gate ◽  
Layer Deposition ◽  
High K

scholarly journals A Study on Improvement and Degradation of Si/SiO2Interface Property for Gate Oxide with TiN Metal Gate

2008 ◽  
Vol 9 (1) ◽  
pp. 6-11 ◽  
Author(s):  
Byung-Hyun Lee ◽  
Yong-Il Kim ◽  
Bong-Soo Kim ◽  
Dong-Soo Woo ◽  
Yong-Jik Park ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Metal Gate ◽  
Tin Metal

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Negative Capacitance ◽  
Double Gate ◽  
High K ◽  
Gate Control ◽  
Effect Transistor ◽  
Dimensional Simulation ◽  
The Impact ◽  
Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

Gate-All-Around (GAA) Fully Depleted (FD) Cantilever Channel MOSFET with High-k Dielectric and Metal Gate

2007 ◽  
Vol 995 ◽  
Author(s):  
Sagnik Dey ◽  
Se-Hoon Lee ◽  
Sachin V. Joshi ◽  
Prashant Majhi ◽  
Sanjay K. Banerjee
Keyword(s):  
Metal Gate ◽  
Leakage Currents ◽  
Drive Current ◽  
Fully Depleted ◽  
Low Leakage ◽  
High Drive ◽  
High K ◽  
High K Dielectric

AbstractA MOSFET formed by a Si cantilever channel suspended between source/drain “anchors” wrapped all-around by high-κ dielectric and metal gate is demonstrated. The device shows excellent subthreshold characteristics and low leakage currents due to the fully depleted body and the gate-all-around architecture implemented with a high-κ dielectric and metal gate. At the same time this also allows a high drive current due to mobility enhancements arising from volume inversion of the cantilever channel such that a large ION/IOFF is achieved.

scholarly journals Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

2011 ◽  
Vol 6 (2) ◽  
pp. 102-106
Author(s):  
Milene Galeti ◽  
Michele Rodrigues ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Short Channel ◽  
High K ◽  
Analog Performance ◽  
Tin Metal ◽  
High K Dielectric ◽  
The Impact

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

scholarly journals Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

2021 ◽  
Vol 11 (1) ◽  
pp. 240
Author(s):  
Hakkee Jung
Keyword(s):  
Dielectric Constant ◽  
Oxide Film ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Asymmetric Structure ◽  
Double Gate ◽  
High K

In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

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