Online Test Structure for Measuring Young’s Modulus and Residual Stress of the Top Silicon Layer of Silicon-On-Insulator by a Pull-in Approach

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

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Behavior of contact-silicided TFSOI gate structures

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100172036 ◽

1994 ◽

Vol 52 ◽

pp. 860-861

Author(s):

N. David Theodore ◽

Juergen Foerstner ◽

Peter Fejes

Keyword(s):

Semiconductor Device ◽

Series Resistance ◽

Field Effect Transistors ◽

Silicon Layer ◽

Device Fabrication ◽

Silicon On Insulator ◽

Continuous Layer ◽

Buried Oxide ◽

Device Structures ◽

Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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A Flexible PI/Si/SiO2 Piezoresistive Microcantilever for Trace-Level Detection of Aflatoxin B1

Sensors ◽

10.3390/s21041118 ◽

2021 ◽

Vol 21 (4) ◽

pp. 1118

Author(s):

Yuan Tian ◽

Yi Liu ◽

Yang Wang ◽

Jia Xu ◽

Xiaomei Yu

Keyword(s):

Single Crystal ◽

Aflatoxin B1 ◽

Single Crystal Silicon ◽

Silicon Layer ◽

Wheatstone Bridge ◽

Silicon On Insulator ◽

Passivation Layer ◽

Spring Constant ◽

Trace Level ◽

Crystal Silicon

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.

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LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

Fluctuation and Noise Letters ◽

10.1142/s021947750400194x ◽

2004 ◽

Vol 04 (02) ◽

pp. L345-L354 ◽

Cited By ~ 3

Author(s):

Y. HADDAB ◽

V. MOSSER ◽

M. LYSOWEC ◽

J. SUSKI ◽

L. DEMEUS ◽

...

Keyword(s):

Noise Level ◽

Low Voltage ◽

Silicon Layer ◽

Electrical Current ◽

Low Noise ◽

Silicon On Insulator ◽

Technological Parameters ◽

Wide Range ◽

Hall Sensors ◽

Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

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Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

10.21203/rs.3.rs-621286/v1 ◽

2021 ◽

Author(s):

Deivakani M ◽

Sumithra M.G ◽

Anitha P ◽

Jenopaul P ◽

Priyesh P. Gandhi ◽

...

Keyword(s):

Breakdown Voltage ◽

Impact Ionization ◽

Semiconductor Industry ◽

Silicon Layer ◽

Silicon On Insulator ◽

Physical Models ◽

Oxide Semiconductor ◽

Soi Mosfet ◽

P Type ◽

Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

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ChemInform Abstract: Growth of Buried Oxide Layers of Silicon-on-Insulator (SOI) Structures by Thermal Oxidation of the Top Silicon Layer.

ChemInform ◽

10.1002/chin.199743021 ◽

2010 ◽

Vol 28 (43) ◽

pp. no-no

Author(s):

E. SCHROER ◽

S. HOPFE ◽

Q. Y. TONG ◽

U. GOESELE ◽

W. SKORUPA

Keyword(s):

Thermal Oxidation ◽

Silicon Layer ◽

Silicon On Insulator ◽

Oxide Layers ◽

Buried Oxide

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A new type of silicon-on-insulator with a perfect surface silicon layer

Ion Implantation Technology–92 ◽

10.1016/b978-0-444-89994-1.50044-2 ◽

1993 ◽

pp. 204-205

Author(s):

Jianming Li ◽

Ming Chong ◽

Jiancheng Zhu

Keyword(s):

Silicon Layer ◽

Silicon On Insulator ◽

New Type

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Non-Destructive Assessment of Thin Film Stresses and Crystal Qualify of Silicon on Insulator Materials with Raman Spectroscopy

MRS Proceedings ◽

10.1557/proc-188-53 ◽

1990 ◽

Vol 188 ◽

Cited By ~ 4

Author(s):

Ingrid De Wolf ◽

Jan Vanhellemont ◽

Herman E. Maes

Keyword(s):

Thin Film ◽

Electron Microscopy ◽

Raman Spectroscopy ◽

Cross Section ◽

Silicon Layer ◽

Silicon On Insulator ◽

Micro Raman Spectroscopy ◽

Transmission Electron ◽

Non Destructive ◽

Zone Melt

ABSTRACTMicro Raman spectroscopy (RS) is used to study the crystalline quality and the stresses in the thin superficial silicon layer of Silicon-On-Insulator (SO) materials. Results are presented for SIMOX (Separation by IMplanted OXygen) and ZMR (Zone Melt Recrystallized) substrates. Both as implanted and annealed SIMOX structures are investigated. The results from the as implanted structures are correlated with spectroscopic ellipsometry (SE) and cross-section transmission electron microscopy (TEM) analyses on the same material. Residual stress in ZMR substrates is studied in low- and high temperature gradient regions.

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Thermal Conductivity of Ultra Thin Single Crystal Silicon Layers: Part II — Experimental Data and Modeling at High Temperatures

Heat Transfer, Volume 2 ◽

10.1115/imece2004-62107 ◽

2004 ◽

Cited By ~ 1

Author(s):

Wenjun Liu ◽

Mehdi Asheghi ◽

K. E. Goodson

Keyword(s):

Experimental Data ◽

Thermal Conductivity ◽

Single Crystal ◽

High Temperatures ◽

Single Crystal Silicon ◽

Silicon Layer ◽

Silicon On Insulator ◽

Boltzmann Transport ◽

Crystal Silicon ◽

Strained Si

Simulations of the temperature field in Silicon-on-Insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This work presents the first experimental data for 20 and 100 nm thick single crystal silicon layers at high temperatures and develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to temperatures range 300–1000 K for silicon layer thicknesses from 10 nm to 1 μm (and even bulk) and agrees well with the experimental data. In addition, the model has an excellent agreement with the predictions of thin film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation, although it is significantly more robust and convenient for integration into device simulators. The experimental data and predictions are required for accurate thermal simulation of the semiconductor devices, nanostructures and in particular the SOI and strained-Si transistors.

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