Passive Voltage Contrast Technique for Rapid In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology

1998 ◽  
Author(s):  
Victor Liang ◽  
Harlan Sur ◽  
Subhas Bothra
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Relative Magnitude ◽  
Deep Submicron ◽  
Process Step ◽  
First Case ◽  
Contrast Technique ◽  
Rapid Characterization ◽  
Voltage Contrast

Abstract Three case studies in which the passive voltage contrast technique (PVC) was used in-fab during the development of a 0.25mm ASIC CMOS technology for rapid characterization and failure isolation are presented. The first case involved using the PVC technique to evaluate the gate oxide quality at different points of the process, allowing for quick identification of the process steps that were damaging the gate oxide and the relative magnitude of the damage that each process step contributed. PVC was then used to perform in-line evaluation of the split lots that were ran to address the problem without having to pull wafers off the line for electrical testing. In the second case study, PVC was used in-line to identify the source of siliciderelated gate-to-source/drain leakage. At this point of the process, electrical probing was not possible, and PVC circumvented this problem. The third case involved using PVC to help identify a new failure mechanism for tungsten plug vias that manifested itself due to plasma charging and layout peculiarities related to deep submicron design rules.

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

2002 ◽  
Author(s):  
Ming-Dou Ker ◽  
Chung-Yu Wu ◽  
Hun-Hsien Chang ◽  
Chien-Chang Huang ◽  
Chau-Neng Wu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron

He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications

2001 ◽  
Vol 37 (12) ◽  
pp. 788 ◽  
Author(s):  
Shyh-Fann Ting ◽  
Yean-Kuen Fang ◽  
Chien-Hao Chen ◽  
Chih-Wei Yang ◽  
Mo-Chiun Yu ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Remote Plasma ◽  
Plasma Nitridation ◽  
Technology Applications ◽  
Submicron Cmos ◽  
Thin Gate Oxide

Defect Isolation and Characterization in Contacts by Using Primary Voltage Adjustment

2003 ◽  
Author(s):  
Yuan-Shih Chen ◽  
Jeng-Han Lee
Keyword(s):  
Cmos Technology ◽  
Primary Energy ◽  
Site Isolation ◽  
Popular Method ◽  
Isolation And Characterization ◽  
Contrast Condition ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Failure Site

Abstract Voltage contrast(VC) is a popular method for failure site isolation[1]. After study we find some weakness on tradition voltage contrast. This paper presents a new voltage contrast procedure that can conquer the weakness. For a CMOS technology, there are four kinds of contact node were used. They are N+/PW node, P+/NW node , poly gate node and well node. Traditional voltage contrast condition uses constant SEM primary energy like 1KV can not distinguish these four kinds of node well. For example a contact lead to P+/NW will be bright in tradition VC[2], but a contact connected to well will also be bright. It means tradition VC can not distinguish difference between contact lead to P+/NW and contact lead to well. To improve the weakness of the traditional VC, we will present a new Voltage Contrast technique, which could distinguish all contact types in CMOS technology.

Effect of the pre-gate oxide cleaning temperature on the reliability of GOI and devices performances in deep submicron CMOS technology

2008 ◽  
Vol 48 (11-12) ◽  
pp. 1786-1790 ◽  
Author(s):  
Y.T. Chiang ◽  
Y.K. Fang ◽  
Y.J. Huang ◽  
T.H. Chou ◽  
S.Y. Yeh ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Submicron Cmos

Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology

2000 ◽  
Author(s):  
Song Zhigang ◽  
Loh Sock Khim ◽  
Shailesh Redkar
Keyword(s):  
Random Access ◽  
Gate Oxide ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Emission Analysis ◽  
Gate Oxides ◽  
Mos Devices ◽  
Voltage Contrast ◽  
Metal Layers

Abstract With further miniaturization of MOS devices, the thickness of gate oxides becomes thinner and thus more sensitive to damage. Emission microscopy has shown its capability in analysis of these failures. However, emission site is not always the exact location of the physical defect. High-density devices with multi-metal layers make the situation worse. But when it is combined with Passive Voltage Contrast (PVC) technique, the success rate of isolating such failures can be greatly increased. In a case study, a unit of 1M bits Static Random Access Memory (SRAM), fabricated by 0.25 µm technology with 5 metal layers, failed after 500 hours burn-in. We successfully isolated the leaky poly and subsequently found gate oxide pinholes with the combination of PVC technique and emission analysis.

Deep Submicron CMOS Technology Using Top-Edge Round STI and Dual Gate Oxide for Low Power 256 M-Bit Mobile DRAM

2003 ◽  
Vol 42 (Part 1, No. 4B) ◽  
pp. 1892-1896 ◽  
Author(s):  
Chihoon Lee ◽  
Donggun Park ◽  
Namhyuk Jo ◽  
Chanseong Hwang ◽  
Hyeong Joon Kim ◽  
...  
Keyword(s):  
Low Power ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Dual Gate ◽  
Submicron Cmos

Fault Isolation of MOL and FEOL Buried Defects Using Conductive Atomic Force Microscopy as a Complement to Passive Voltage Contrast Imaging

2017 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Cmos Technology ◽  
Fault Isolation ◽  
Contrast Imaging ◽  
Conductive Atomic Force Microscopy ◽  
Isolation Technique ◽  
Conductive Afm ◽  
Force Microscopy ◽  
Atomic Force ◽  
Voltage Contrast

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.

Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques for Deep Sub-Micron CMOS Leaky Gate Detection

2000 ◽  
Author(s):  
Fred Y. Chang ◽  
Victer Chan
Keyword(s):  
Case Studies ◽  
Detection Technique ◽  
Cobalt Silicide ◽  
Process Technology ◽  
Process Flow ◽  
Voltage Contrast ◽  
Emission Detection ◽  
Wet Etch ◽  
Direct Confirmation

Abstract This paper describes a novel de-process flow by combining cobalt silicide / nitride wet etch with KOH electrochemical wet etch (ECW) to identify leaky gate in silicided deep sub-micron process technology. Traditionally, leaky gate identification requires direct confirmation by gate level electrical or emission detection technique. Ohtani [1] used KOH electrochemical etch application to identify nonsilicided leaky gate capacitor in DRAM without using the above confirmation. The result of the case study demonstrates the expanded application of ECW etch to both silicided 0.18um logic and SRAM devices. Voltage contrast at metal 1 to assist leaky gate localization is also proposed. By combining both techniques, the possibility for isolating gate related defects are greatly enhanced. Case studies also show the advantages of the proposed technique over conventional poly level voltage contrast in leaky gate identification especially with devices that use local interconnect and nitride liner process.

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

2003 ◽  
Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Fault Isolation ◽  
Electronic Information ◽  
Scan Testing ◽  
Challenging Environment ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Higher Sensitivity

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

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