FUNDAMENTALS OF THE SQUEEZE-FLOW BETWEEN A HEAT SINK AND A FLIP-CHIP

2008 ◽  
Vol 32 (3-4) ◽  
pp. 467-486 ◽  
Author(s):  
M.A. Marois ◽  
M. Lacroix
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
String Model ◽  
Thermal Interface Material ◽  
Squeeze Flow ◽  
Back Side ◽  
Two Dimensional ◽  
Particle Volume ◽  
Volume Fractions ◽  
Drop Flow

The paper presents the fundamentals of the squeeze-flow of the thermal interface material (TIM) that takes place during the pressing of a heat sink to the back side of a flip-chip is studied. A two-dimensional string model is developed for predicting the time-varying plate separation and squeeze-rate in terms of the squeeze force. The predictions are compared to a one-dimensional string model and to a squeeze-drop flow model. Results indicate that the flow resulting from the squeezing of a string of TIM between two rigid plates is truly two-dimensional. The effect of surface tension and of the heat transfer is found to be negligible under the assembly conditions. The flow behaviour of the TIM with suspensions of high thermal conductivity particles is also investigated. It is shown that the fluid remains Newtonian for particle volume fractions smaller than 30%. For volume fractions larger than 30%, the fluid becomes Non-Newtonian during the early stages of the squeezing process, i.e. for t ≤ 1s. In the later stages however (t > 10s), the fluid may be considered Newtonian.

Numerical Study of Forced Convection of Nanofluids in a Microchannel Heat Sink

2008 ◽  
Author(s):  
Parisa Vaziee ◽  
Omid Abouali
Keyword(s):  
Heat Transfer ◽  
Pressure Drop ◽  
Heat Sink ◽  
Volume Fraction ◽  
Numerical Study ◽  
Heat Removal ◽  
Al2o3 Nanoparticles ◽  
Microchannel Heat Sink ◽  
Particle Volume ◽  
Volume Fractions

Effectiveness of the microchannel heat sink cooled by nanofluids with various particle volume fractions is investigated numerically using the latest theoretical models for conductivity and viscosity of the nanofluids. Both laminar and turbulent flows are considered in this research. The model of conductivity used in this research accounts for the fundamental role of Brownian motion of the nanoparticles which is in good agreement with the experimental data. The changes in viscosity of the nanofluid due to temperature variation are considered also. Final results are compared with the experimental measurements for heat transfer coefficient and pressure drop in microchannel. Enhancement in heat transfer is achieved for laminar flow with increasing of volume fraction of Al2O3 nanoparticles. But for turbulent flow an enhancement of heat removal was not seen and using higher volume fractions of nanoparticles increases the maximum substrate temperature. Pressure drop is increased with using nanofluids because of the augmentation in the viscosity and this increase is more noticeable in higher Reynolds numbers.

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Wear Behavior of In Situ Mg2Si Particle-Dispersed Magnesium Alloys

2017 ◽  
Vol 909 ◽  
pp. 100-105
Author(s):  
Kazunori Asano
Keyword(s):  
Magnesium Alloys ◽  
High Speed ◽  
Wear Behavior ◽  
Particle Dispersion ◽  
Dry Sliding Wear ◽  
Wear Loss ◽  
Mg2si Particle ◽  
Particle Volume ◽  
Volume Fractions

Magnesium alloys, in which the in-situ Mg2Si particles were dispersed, were fabricated by a casting process, and the dry sliding wear behavior of the alloys was investigated. Optical microscopy revealed that the polygonal Mg2Si particles were homogeneously dispersed in the alloys. Mg2Si particle volume fractions in the alloys were 7 and 11 vol%. Although the wear loss of the alloy decreased due to the particle-dispersion, there was no difference in the wear loss between the alloys with different volume fractions. The worn surfaces of the particle-dispersed alloys were covered with the crumbled Mg2Si particles, which would prevent seizure between the alloy and the steel counterpart, leading to an improvement in the wear resistance of the alloy. The particle-dispersion slightly decreased the scatter of the coefficient of friction during the wear for the low sliding speed and load, but the effect of the dispersion was not clearly observed for the high speed and load.

The Influence of Multiple Inclusions on the Cauchy Stress of a Spherical Particle-Reinforced Composite Under Uniaxial Loading

2014 ◽  
Author(s):  
Ke Niu ◽  
Armin Abedini ◽  
Zengtao Chen
Keyword(s):  
Spherical Particle ◽  
Single Particle ◽  
Volume Fraction ◽  
Unit Cell ◽  
Spherical Particles ◽  
Uniaxial Tensile ◽  
Cauchy Stress ◽  
Particle Volume ◽  
Volume Fractions ◽  
Unit Cells

This paper investigates the influence of multiple inclusions on the Cauchy stress of a spherical particle-reinforced metal matrix composite (MMC) under uniaxial tensile loading condition. The approach of three-dimensional cubic multi-particle unit cell is used to investigate the 15 non-overlapping identical spherical particles which are randomly distributed in the unit cell. The coordinates of the center of each particle are calculated by using the Random Sequential Adsorption algorithm (RSA) to ensure its periodicity. The models with reinforcement volume fractions of 10%, 15%, 20% and 25% are evaluated by using the finite element method. The behaviour of Cauchy stress for each model is analyzed at a far-field strain of 5%. For each reinforcement volume fraction, four models with different particle spatial distributions are evaluated and averaged to achieve a more accurate result. At the same time, single-particle unit cell and analytical model were developed. The stress-strain curves of multi-particle unit cells are compared with single-particle unit cells and the tangent homogenization model coupled with the Mori-Tanaka method. Only little scatters were found between unit cells with the same particle volume fractions. Multi-particle unit cells predict higher response than single particle unit cells. As the volume fraction of reinforcements increases, the Cauchy stress of MMCs increases.

scholarly journals Optimisation of a microelectronic assembly package using response surface methodology

2021 ◽  
Vol 39 (4) ◽  
pp. 1058-1065
Author(s):  
M. Ekpu
Keyword(s):  
Response Surface Methodology ◽  
Thermal Resistance ◽  
Response Surface ◽  
Heat Sink ◽  
Chip Thickness ◽  
Thermal Interface Material ◽  
Resistance Response ◽  
Temperature Solution ◽  
Design Software ◽  
Central Composite

This article addressed heat conduction in microelectronics applications. ANSYS finite element design software was used to design the model, while Design Expert software was used for the response surface methodology (RSM) analysis. The components analysed were heat-sink base (HSB) thickness, thermal interface material (TIM) thickness, and chip thickness. A design of experiment comprising of 15 central composite design (CCD) for the coded levels (low (-) and high (+)) of the factors were generated. Heat flow was applied to the chip while a convective coefficient was applied to the heat-sink. The temperature solution was used to calculate the thermal resistance response for the 15 CCD experimental runs. The results from the RSM study proposed an optimal (minimization analysis) combination of 3.5 mm, 0.04 mm, and 0.75 mm, for HSB thickness, TIM thickness, and chip thickness respectively. While the optimal mean thermal resistance of 0.31052 K/W was achieved from the proposed optimal parameters. Keywords: RSM; CCD; thermal resistance; temperature; microelectronics

scholarly journals Demonstration of a Compliant Micro-Spring Array As a Thermal Interface Material for Pluggable Optoelectronic Transceiver Modules

2019 ◽  
Author(s):  
Jin Cui ◽  
Liang Pan ◽  
Justin A. Weibel
Keyword(s):  
Heat Sink ◽  
Thermal Contact ◽  
Thermal Conductance ◽  
Thermal Interface Material ◽  
Thermal Contact Conductance ◽  
Compression Pressure ◽  
Thermal Interface ◽  
Operation Temperature ◽  
Optical Module ◽  
Dry Contact

Abstract Pluggable optoelectronic transceiver modules are widely used in the fiber-optic communication infrastructure. It is essential to mitigate thermal contact resistance between the high-power optical module and its riding heat sink in order to maintain the required operation temperature. The pluggable nature of the modules requires dry contact thermal interfaces that permit repeated insertion–disconnect cycles under low compression pressures (∼10–100 kPa). Conventional wet thermal interface materials (TIM), such as greases, or those that require high compression pressures, are not suitable for pluggable operation. Here we demonstrate the use of compliant micro-structured TIM to enhance the thermal contact conductance between an optical module and its riding heat sink under a low compression pressure (20 kPa). The metallized and polymer-coated structures are able to accommodate the surface nonflatness and microscale roughness of the mating surface while maintaining a high effective thermal conductance across the thickness. This dry contact TIM is demonstrated to maintain reliable thermal performance after 100 plug-in and plug-out cycles while under compression.

Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000666-000698
Author(s):  
Christopher Jahnes ◽  
Eric Huenger ◽  
Scott Kisting
Keyword(s):  
Power Distribution ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Back Side ◽  
Thermal Reliability ◽  
Dielectric Layers ◽  
Chip Size ◽  
Package Density ◽  
Silicon Vias ◽  
Wafer Thinning

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Packaging of High Power UV-LED Modules on Ceramic and Aluminum Substrates

2012 ◽  
Vol 2012 (1) ◽  
pp. 000225-000232 ◽  
Author(s):  
Marc Schneider ◽  
Benjamin Leyrer ◽  
Christian Herbold ◽  
Stefan Maikowske
Keyword(s):  
Thermal Resistance ◽  
Heat Sink ◽  
Input Power ◽  
Thermal Interface Material ◽  
Maximum Temperature ◽  
Thermal Interface ◽  
Uv Led ◽  
Forward Current ◽  
Water Cooler ◽  
Forced Air

An LED module consisting of 98 UV-LEDs with an emission wavelength of 395 nm placed on a ceramic substrate of 211 mm2 is presented. The module is cooled by a forced air heat sink as well as a high performance microstructured water cooler to lower the thermal resistance. For high thermal conductance a liquid metal as the thermal interface material between substrate and heat sink is used. With the forced air heat sink a maximum irradiance of 27.3 W/cm2 at a forward current of 700 mA and 220 W electrical input power was achieved. The microstructured water cooler enabled an almost doubling of the electrical input power (430 W) while maintaining the chip's maximum temperature. For a reduction of the module's thermal resistance a thick film process for aluminum sheet metal substrates was developed. A prototype LED module with 25 UV-LED chips on an area of 54 mm2 achieved a maximum optical power density of 31.6 W/cm2 at a forward current of 900 mA using a forced air heat sink. For an improved cooling of the LED chips a chip-on-heat sink-technology with embedded water cooling channels is developed to eliminate the thermal interface between substrate and heat sink.

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