scholarly journals Analysis of Electrical Characteristics in 4H-SiC Trench-Gate MOSFETs with Grounded Bottom Protection p-Well Using Analytical Modeling

2021 ◽  
Vol 11 (24) ◽  
pp. 12075
Author(s):  
Jee-Hun Jeong ◽  
Ogyun Seok ◽  
Ho-Jun Lee
Keyword(s):  
Analytical Model ◽  
Computer Aided Design ◽  
Analytical Modeling ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Characteristics ◽  
Reverse Transfer ◽  
Tcad Simulation ◽  
Switching Characteristics ◽  
Aided Design

A new analytical model to analyze and optimize the electrical characteristics of 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors (TMOSFETs) with a grounded bottom protection p-well (BPW) was proposed. The optimal BPW doping concentration (NBPW) was extracted by analytical modeling and a numerical technology computer-aided design (TCAD) simulation, in order to analyze the breakdown mechanisms for SiC TMOSFETs using BPW, while considering the electric field distribution at the edge of the trench gate. Our results showed that the optimal NBPW obtained by analytical modeling was almost identical to the simulation results. In addition, the reverse transfer capacitance (Cgd) values obtained from the analytical model correspond with the results of the TCAD simulation by approximately 86%; therefore, this model can predict the switching characteristics of the effect BPW regions.

scholarly journals Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1422
Author(s):  
Ki-Yeong Kim ◽  
Joo-Seok Noh ◽  
Tae-Young Yoon ◽  
Jang-Hyun Kim
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Buffer Layers ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Insulated Gate Bipolar Transistor ◽  
Computer Aided ◽  
Long Time ◽  
Tcad Simulation ◽  
Aided Design

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.

scholarly journals Unidirectional Operation of p-GaN Gate AlGaN/GaN Heterojunction FET Using Rectifying Drain Electrode

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 291
Author(s):  
Tae-Hyeon Kim ◽  
Won-Ho Jang ◽  
Jun-Hyeok Yim ◽  
Ho-Young Cha
Keyword(s):  
Computer Aided Design ◽  
Process Step ◽  
Maximum Current ◽  
Blocking Device ◽  
Drain Electrode ◽  
Additional Process ◽  
Effect Transistor ◽  
Tcad Simulation ◽  
Switching Characteristics ◽  
Aided Design

In this study, we proposed a rectifying drain electrode that was embedded in a p-GaN gate AlGaN/GaN heterojunction field-effect transistor to achieve the unidirectional switching characteristics, without the need for a separate reverse blocking device or an additional process step. The rectifying drain electrode was implemented while using an embedded p-GaN gating electrode that was placed in front of the ohmic drain electrode. The embedded p-GaN gating electrode and the ohmic drain electrode are electrically shorted to each other. The concept was validated by technology computer aided design (TCAD) simulation along with an equivalent circuit, and the proposed device was demonstrated experimentally. The fabricated device exhibited the unidirectional characteristics successfully, with a threshold voltage of ~2 V, a maximum current density of ~100 mA/mm, and a forward drain turn-on voltage of ~2 V.

scholarly journals Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example

Materials ◽  
2022 ◽  
Vol 15 (2) ◽  
pp. 457
Author(s):  
Zhaoxiang Wei ◽  
Hao Fu ◽  
Xiaowen Yan ◽  
Sheng Li ◽  
Long Zhang ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Impact Ionization ◽  
Field Effect Transistors ◽  
Vertical Channel ◽  
Ionization Rate ◽  
Oxide Semiconductor ◽  
Inclined Channel ◽  
Device Structures ◽  
Aided Design ◽  
Impact Ionization Rate

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

scholarly journals 4H-SiC Double-Trench MOSFET with Side Wall Heterojunction Diode for Enhanced Reverse Recovery Performance

Energies ◽  
2020 ◽  
Vol 13 (18) ◽  
pp. 4602
Author(s):  
Junghun Kim ◽  
Kwangsoo Kim
Keyword(s):  
Computer Aided Design ◽  
Side Wall ◽  
Oxide Semiconductor ◽  
Heterojunction Diode ◽  
Power Module ◽  
Switching Performance ◽  
Conduction State ◽  
Effect Transistor ◽  
Switching Characteristics ◽  
Aided Design

In this study, a novel 4H-SiC double-trench metal-oxide semiconductor field-effect transistor (MOSFET) with a side wall heterojunction diode is proposed and investigated by conducting numerical technology computer-aided design simulations. The junction between P+ polysilicon and the N-drift layer forming a heterojunction diode on the side wall of the source trench region suppresses the operation of the PiN body diode during the reverse conduction state. Therefore, the injected minority carriers are completely suppressed, reducing the reverse recovery current by 73%, compared to the PiN body diodes. The switching characteristics of the proposed MOSFET using the heterojunction diode as a freewheeling diode was compared to the power module with a conventional MOSFET and an external diode as a freewheeling diode. It is shown that the switching performance of the proposed structure exhibits equivalent characteristics compared to the power module, enabling the elimination of an external freewheeling diode in the power system.

scholarly journals Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

2020 ◽  
Vol 10 (24) ◽  
pp. 8880
Author(s):  
Min Woo Kang ◽  
Woo Young Choi
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Gate Insulator ◽  
Radius Of Curvature ◽  
Computer Aided ◽  
Simulation Results ◽  
Tcad Simulation ◽  
Aided Design

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

scholarly journals A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 164
Author(s):  
Ke Han ◽  
Shanglin Long ◽  
Zhongliang Deng ◽  
Yannan Zhang ◽  
Jiawei Li
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Source Voltage ◽  
Effect Transistor ◽  
Supply Current ◽  
Aided Design

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

TCAD SIMULATION AND PERFORMANCE ANALYSIS OF SINGLE AND DUAL GATE OTFTs

2019 ◽  
Vol 27 (05) ◽  
pp. 1950145 ◽  
Author(s):  
A. D. D. DWIVEDI ◽  
POOJA KUMARI
Keyword(s):  
Performance Analysis ◽  
Computer Aided Design ◽  
Simulation Software ◽  
Electrical Characteristics ◽  
Organic Thin Film ◽  
Dual Gate ◽  
Tcad Simulation ◽  
Numerical Device ◽  
And Performance ◽  
Aided Design

This paper presents finite element-based numerical simulation and performance analysis of dual and single gate pentacene-based organic thin film transistors (OTFTs) using technology computer-aided design (TCAD) tools. Electrical characteristics of the devices have been simulated using 2D numerical device simulation software ATLAS™ from Silvaco International. Also, device parameters like threshold voltage, mobility, transconductance, subthreshold swing and current on/off ratio of the single and dual gate OTFTs have been extracted and compared.

Analysis of Channel Area Fluctuation Effects of Gate-All-Around Tunnel Field-Effect Transistor

2020 ◽  
Vol 20 (7) ◽  
pp. 4409-4413
Author(s):  
Seok Jung Kang ◽  
Jeong-Uk Park ◽  
Kyung Jin Rim ◽  
Yoon Kim ◽  
Jang Hyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Oxide Semiconductor ◽  
Fluctuation Effects ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
Aided Design ◽  
First Time

In this manuscript, channel area fluctuation (CAF) effects on turn-on voltage (Von) and subthreshold swing (SS) in gate-all-around (GAA) nanowire (NW) tunnel field-effect transistor (TFET) with multi-bridge-channel (MBC) have been investigated for the first time. These variations occur because oblique etching slope makes various elliptical-shaped channels in MBC-TFET. Since TFET is promising candidates to succeed metal-oxide-semiconductor FETs (MOSFET), these variation effects have been compared to MOSFET. Furthermore, Ge homojunction TFET, one of the solutions to increase on-state current in TFET and improve SS also has been simulated using technology computer-aided design (TCAD) simulation. The results would be worth reference for future study about GAA NW TFETs.

scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

Sign in / Sign up

Export Citation Format

Share Document