Online Nonlinear Error Compensation Circuit Based on Neural Networks

Nonlinear errors of sensor output signals are common in the field of inertial measurement and can be compensated with statistical models or machine learning models. Machine learning solutions with large computational complexity are generally offline or implemented on additional hardware platforms, which are difficult to meet the high integration requirements of microelectromechanical system inertial sensors. This paper explored the feasibility of an online compensation scheme based on neural networks. In the designed solution, a simplified small-scale network is used for modeling, and the peak-to-peak value and standard deviation of the error after compensation are reduced to 17.00% and 16.95%, respectively. Additionally, a compensation circuit is designed based on the simplified modeling scheme. The results show that the circuit compensation effect is consistent with the results of the algorithm experiment. Under SMIC 180 nm complementary metal-oxide semiconductor (CMOS) technology, the circuit has a maximum operating frequency of 96 MHz and an area of 0.19 mm2. When the sampling signal frequency is 800 kHz, the power consumption is only 1.12 mW. This circuit can be used as a component of the measurement and control system on chip (SoC), which meets real-time application scenarios with low power consumption requirements.

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Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations

Materials ◽

10.3390/ma12172745 ◽

2019 ◽

Vol 12 (17) ◽

pp. 2745 ◽

Cited By ~ 6

Author(s):

Luis Camuñas-Mesa ◽

Bernabé Linares-Barranco ◽

Teresa Serrano-Gotarredona

Keyword(s):

Neural Networks ◽

Learning Strategies ◽

Large Scale ◽

Sensory Information ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Hardware Implementations ◽

Learning Capabilities ◽

Promising Solution

Inspired by biology, neuromorphic systems have been trying to emulate the human brain for decades, taking advantage of its massive parallelism and sparse information coding. Recently, several large-scale hardware projects have demonstrated the outstanding capabilities of this paradigm for applications related to sensory information processing. These systems allow for the implementation of massive neural networks with millions of neurons and billions of synapses. However, the realization of learning strategies in these systems consumes an important proportion of resources in terms of area and power. The recent development of nanoscale memristors that can be integrated with Complementary Metal–Oxide–Semiconductor (CMOS) technology opens a very promising solution to emulate the behavior of biological synapses. Therefore, hybrid memristor-CMOS approaches have been proposed to implement large-scale neural networks with learning capabilities, offering a scalable and lower-cost alternative to existing CMOS systems.

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Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

Jurnal Teknologi ◽

10.11113/jt.v67.2054 ◽

2014 ◽

Vol 67 (1) ◽

Author(s):

Wong How Hwan ◽

Vinny Lam Siu Fan ◽

Yusmeeraz Yusof

Keyword(s):

Power Consumption ◽

Low Power ◽

Dna Hybridization ◽

Point Of Care ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Channel Length ◽

Electrical Signal ◽

Oxide Semiconductor ◽

Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool.

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A new design for 4-bit RCA using Quantum Cellular Automata Technology

10.21203/rs.3.rs-569937/v1 ◽

2021 ◽

Author(s):

Saeid Seyedi ◽

Behrouz Pourghebleh

Keyword(s):

Cellular Automata ◽

Power Consumption ◽

Cell Count ◽

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Quantum Cellular Automata ◽

Ripple Carry Adder ◽

Efficient Alternative

Abstract Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology due to its excellent potential in developing designs with low-power consumption, high-speed, and high-density has been recognized as a suitable replacement to CMOS technology. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. Adders as the main unit in logic circuits and digital arithmetic play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and due to its remarkable features can be useful to reach circuits with the minimum required area and power consumption. Therefore, in this study, a new design for RCA in QCA technology is recommended to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner version 2.0.3 as a well known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count in comparison to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.

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Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2022.39908 ◽

2022 ◽

Vol 10 (1) ◽

pp. 732-737

Author(s):

Prakash Sharma

Keyword(s):

Power Consumption ◽

Phase Noise ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Ring Oscillator ◽

Oxide Semiconductor ◽

Center Frequency ◽

Noise Power ◽

Ring Oscillators ◽

Voltage Controlled Oscillator

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

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New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Micromachines ◽

10.3390/mi10060368 ◽

2019 ◽

Vol 10 (6) ◽

pp. 368 ◽

Cited By ~ 8

Author(s):

Giulia Santoro ◽

Giovanna Turvani ◽

Mariagrazia Graziano

Keyword(s):

Power Consumption ◽

High Performance ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Point Of View ◽

Oxide Semiconductor ◽

Strong Impact ◽

Technological Advancement ◽

Data Movement ◽

Memory Wall

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

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Monolithic-3D (M3D) Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical (CMOS-NEM) Hybrid Reconfigurable Logic (RL) Circuits

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2020.17790 ◽

2020 ◽

Vol 20 (7) ◽

pp. 4176-4181

Author(s):

Ji Wang Ko ◽

Woo Young Choi

Keyword(s):

Metal Oxide ◽

Power Consumption ◽

Three Dimensional ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Reconfigurable Logic ◽

Signal Transfer ◽

Technology Node

Monolithic-three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) hybrid reconfigurable logic (RL) circuits are compared and analyzed with CMOS-only RL ones in the 130-nm CMOS technology node. M3D CMOS-NEM hybrid RL circuits are superior to CMOS-only ones in terms of power consumption and signal transfer speed thanks to the NEM memory switches. As well as in the routing part, it has many advantages in the logic part following the switch.

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An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽

10.3390/electronics10070804 ◽

2021 ◽

Vol 10 (7) ◽

pp. 804

Author(s):

Gibeom Shin ◽

Kyunghwan Kim ◽

Kangseop Lee ◽

Hyun-Hak Jeong ◽

Ho-Jin Song

Keyword(s):

Power Consumption ◽

Frequency Band ◽

Noise Figure ◽

Complementary Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Operating Frequency ◽

Variable Gain Amplifier ◽

Variable Gain ◽

Operating Frequency Band ◽

Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

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Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

Dalton Transactions ◽

10.1039/d1dt00731a ◽

2021 ◽

Vol 50 (16) ◽

pp. 5540-5551

Author(s):

Almudena Notario-Estévez ◽

Xavier López ◽

Coen de Graaf

Keyword(s):

Metal Oxide ◽

Computational Study ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Molecular Conduction ◽

Conduction Properties ◽

Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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