scholarly journals Low-Power Highly Robust Resistance-to-Period Converter

Sensors ◽  
2018 ◽  
Vol 19 (1) ◽  
pp. 8
Author(s):  
Luis Álvarez-Simón ◽  
Emmanuel Gómez-Ramírez ◽  
María Sanz-Pascual
Keyword(s):  
Low Power ◽  
Output Signal ◽  
Supply Voltage ◽  
High Accuracy ◽  
Cmos Process ◽  
Temperature Variations ◽  
Signal Variation ◽  
Novel Structure ◽  
Voltage Variation ◽  
Complex Circuits

This paper presents a novel structure of Resistance- to-Period (R-T) Converter highly robust to supply and temperature variations. Robustness is achieved by using the ratiometric approach so that complex circuits or high accuracy voltage references are not necessary. To prove the proposed architecture of R-T converter, a prototype was implemented in a 0.18 μ m CMOS process with a single supply voltage of 1.8 V and without any stable reference voltage. Experimental results show a maximum ±1.5% output signal variation for ±10% supply voltage variation and in a 3–95 ° C temperature range.

scholarly journals A High-Accuracy Ultra-Low-Power Offset-Cancelation On-Off Bandgap Reference for Implantable Medical Electronics

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 814 ◽  
Author(s):  
Jiangtao Xu ◽  
Yawei Wang ◽  
Minshun Wu ◽  
Ruizhi Zhang ◽  
Sufen Wei ◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Sampling Strategy ◽  
High Accuracy ◽  
Cmos Process ◽  
Medical Electronics ◽  
Bandgap Reference ◽  
Ultra Low Power ◽  
Voltage Range ◽  
Average Current

An ultra-low-power and high-accuracy on-off bandgap reference (BGR) is demonstrated in this paper for implantable medical electronics. The proposed BGR shows an average current consumption of 78 nA under 2.8 V supply and an output voltage of 1.17 V with an untrimmed accuracy of 0.69%. The on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power consumption and noise. The on-off mechanism allows a relatively higher current in the sample phase to alleviate the process variation of bipolar transistors. To compensate the error caused by operational amplifier offset, the correlated double sampling strategy is adopted in the BGR. The proposed BGR is implemented in 0.35 μm standard CMOS process and occupies a total area of 0.063 mm2. Measurement results show that the circuit works properly in the supply voltage range of 1.8–3.2 V and achieves a line regulation of 0.59 mV/V. When the temperature varies from −20 to 80 °C, an average temperature coefficient of 19.6 ppm/°C is achieved.

A NOVEL WIDEBAND CMOS VCO USING SWITCH CAPACITORS ARRAY FOR RF APPLICATIONS

2012 ◽  
Vol 21 (05) ◽  
pp. 1250046
Author(s):  
MOHAMMAD NIABOLI-GUILANI ◽  
MAHROKH MAGHSOODI ◽  
ALIREZA SABERKARI ◽  
REZA MESHKIN
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Tuning Range ◽  
High Efficiency ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Voltage Variation ◽  
Low Power Dissipation ◽  
Tuning Frequency

This paper presents a novel low power consumption, low phase noise, and high tuning range CMOS cross-coupled voltage-controlled oscillator (VCO). Using common mode double-pseudo-resistance technique in the proposed circuit leads to low power dissipation without degrading the phase noise. Additionally, band-switching capacitor array is employed in order to increase the tuning range. The schematic circuit of the proposed VCO is simulated in 0.18 μm 1P6M CMOS process and simulation results show high efficiency of the proposed circuit. The overall tuning frequency range is from 1.7 GHz to 3.18 GHz (59%) with tuning voltage variation range from 0 V to 1.5 V. The proposed VCO circuit has phase noise of -102.6 and -124.3 dBc/Hz at 100 KHz and 1 MHz offset frequency from the carrier, respectively, while consumes 1.98 mW power at 1.5 V supply voltage.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

Design and Implementation of a High Accuracy Interpolation Encoder IC for Magnetic Sensor

2019 ◽  
Author(s):  
Wen-Yu Chen ◽  
Yi-Feng Zhang ◽  
Paul C.-P. Chao ◽  
Eka Fitrah Pribadi
Keyword(s):  
Measurement System ◽  
Noise Immunity ◽  
Supply Voltage ◽  
High Accuracy ◽  
Cmos Process ◽  
Specific Method ◽  
Clock Frequency ◽  
Design And Implementation ◽  
Equal Distance ◽  
Interpolation Technique

Abstract The magnetic encoder (ME) always employs sensor passing through periodic and equal distance grating and then generates periodic quadrature scaling signals for displacement measurement. The phase is relative to the movement. To improve encoder accuracy or resolution, electronic interpolation technique had been developed to subdivide the phase of quadrature scaling signals. According to the trends, this paper proposed a specific method with excellent noise immunity characteristic and a complete calibration process to improve the accuracy of the system. The designed circuit is taped-out using TSMC 0.18-μm CMOS process, where the active area is 1643 μm × 1676 μm. The chip has the specification of 3.3 V supply voltage, 20 MHz clock frequency, and 0.0859 mW power consumption. The accuracy of the measurement system is 1.065um.

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6591
Author(s):  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Shih-Chang Hsia ◽  
S. M. Salahuddin Morsalin ◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Random Access ◽  
Average Energy ◽  
Cmos Process ◽  
Pulse Control ◽  
Power Performance ◽  
Process Technology ◽  
Low Leakage ◽  
Noise Margin

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

scholarly journals A 920-MHz Dual-Mode Receiver with Energy Harvesting for UHF RFID Tag and IoT

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1042
Author(s):  
Peiqing Han ◽  
Zhaofeng Zhang ◽  
Yajun Xia ◽  
Niansong Mei
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
High Sensitivity ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Dual Mode ◽  
Operating Modes ◽  
On Chip

A low-power dual-mode receiver is presented for ultra-high-frequency (UHF) radio frequency identification (RFID) systems. The reconfigurable architecture of the tag is proposed to be compatible with low-power and high-sensitivity operating modes. The read range of RFID system and the lifetime of the tag are increased by photovoltaic, thermoelectric and RF energy-harvesting topology. The receiver is implemented in a 0.18-μm standard CMOS process and occupies an active area of 0.65 mm × 0.7 mm. For low-power mode, the tag is powered by the rectifier and the sensitivity is −18 dBm. For high-sensitivity mode, the maximum PCE of the fully on-chip energy harvester is 46.5% with over 1-μW output power and the sensitivity is −40 dBm with 880 nW power consumption under the supply voltage of 0.8 V.

Sign in / Sign up

Export Citation Format

Share Document