scholarly journals A Digital Interface ASIC for Triple-Axis MEMS Vibratory Gyroscopes

Sensors ◽  
2020 ◽  
Vol 20 (19) ◽  
pp. 5460 ◽  
Author(s):  
Risheng Lv ◽  
Qiang Fu ◽  
Weiping Chen ◽  
Liang Yin ◽  
Xiaowei Liu ◽  
...  
Keyword(s):  
Angular Velocity ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Resonance Oscillation ◽  
Angular Rotation ◽  
Charge Voltage ◽  
Digital Interface ◽  
Vibratory Gyroscopes ◽  
Mems Vibratory Gyroscopes

This paper proposes a solution for sensing spatial angular velocity. A high-performance digital interface application specific integrated circuit (ASIC) for triple-axis micro-electromechanical systems (MEMS) vibratory gyroscopes is presented. The technique of time multiplexing is employed for synergetic stable drive control and precise angular velocity measurement in three separate degrees of freedom (DOF). Self-excited digital closed loop drives the proof mass in sensing elements at its inherent resonant frequency for Coriolis force generation during angular rotation. The analog front ends in both drive and sense loops are comprised of low-noise charge-voltage (C/V) converters and multi-channel incremental zoom analog-to-digital converters (ADC), so that capacitance variation between combs induced by mechanical motion is transformed into digital voltage signals. Other circuitry elements, such as loop controlling and accurate demodulation modules, are all implemented in digital logics. Automatic amplitude stabilization is mainly realized by peak detection and proportion-integration (PI) control. Nonlinear digital gain adjustment is designed for rapid establishment of resonance oscillation and linearity improvement. Manufactured in a standard 0.35-μm complementary metal-oxide-semiconductor (CMOS) technology, this design achieves a bias instability of 2.1°/h and a nonlinearity of 0.012% over full-scale range.

scholarly journals An Interface ASIC for MEMS Vibratory Gyroscopes with Nonlinear Driving Control

Micromachines ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 270 ◽  
Author(s):  
Risheng Lv ◽  
Qiang Fu ◽  
Liang Yin ◽  
Yuan Gao ◽  
Wei Bai ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Resonance Oscillation ◽  
Temperature Drift ◽  
Sigma Delta ◽  
Vibratory Gyroscopes ◽  
Digital Circuitry ◽  
Mems Vibratory Gyroscopes

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm2. Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range.

A Study on Scalability and Variation of CMOS Low Noise Amplifier in Advance CMOS Technology Processes

2016 ◽  
Vol 833 ◽  
pp. 135-139
Author(s):  
Dayang Nur Salmi Dharmiza Awang Salleh ◽  
Rohana Sapawi
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Rf Circuits ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Technology Scaling ◽  
Wireless Applications ◽  
Noise Amplifier ◽  
Technology Processes

Recent technology requires multistandard Radio Frequency (RF) chips for multipurpose wireless applications. In RF circuits, a low-noise amplifier (LNA) plays the key role in determining the receiver’s performance. With CMOS technology scaling, various designs has been adopted to study circuit’s characteristic and variation. In this paper, we present the results of scalable wideband LNA design based on complementary metal oxide semiconductor (CMOS), with its variance study. The design was fabricated in 180nm, 90nm, 65nm and 40nm CMOS technology.

scholarly journals A 24.88 nV/√Hz Wheatstone Bridge Readout Integrated Circuit with Chopper-Stabilized Multipath Operational Amplifier

2020 ◽  
Vol 10 (1) ◽  
pp. 399 ◽  
Author(s):  
Kwonsang Han ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Operational Amplifier ◽  
Wheatstone Bridge ◽  
Input Resistance ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Readout Integrated Circuit ◽  
Chopper Stabilization

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively.

A digital interface integration circuit design for high precision quartz-gyro

2019 ◽  
Vol 33 (19) ◽  
pp. 1950222
Author(s):  
Xinpeng Di ◽  
Weiping Chen ◽  
Xiaowei Liu
Keyword(s):  
Angular Velocity ◽  
High Precision ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Low Noise ◽  
Temperature Drift ◽  
Interface Circuit ◽  
Digital Detection ◽  
Fast Start ◽  
Application Specific Integrated Circuit

A design of digital application specific integrated circuit (ASIC) of quartz-gyro is proposed in this paper. The digital drive circuit with fast-start oscillation and digital detection circuit with low noise are adopted to implement the digital output of the main circuit node and high precision angular velocity detection. The interface circuit is fabricated in a standard 0.35 [Formula: see text]m CMOS technology and test result shows the angular random walk and zero stability are [Formula: see text]/[Formula: see text] and [Formula: see text]/h ([Formula: see text]), respectively. The bias-instability is [Formula: see text]/h (Allen). The nonlinearity is limited to 0.035% and the zero temperature drift is [Formula: see text]/h from [Formula: see text] to [Formula: see text]. The chip exhibits great superiority on the aspects of high precision angular velocity digital detection and temperature characteristics of overall system.

A speed-optimized, low-noise APD with 0.18 μm CMOS technology for the VLC applications

2020 ◽  
Vol 34 (29) ◽  
pp. 2050321
Author(s):  
Wei Wang ◽  
Hong-An Zeng ◽  
Fang Wang ◽  
Guanyu Wang ◽  
Yingtao Xie ◽  
...  
Keyword(s):  
Dark Current ◽  
Complementary Metal Oxide Semiconductor ◽  
Visible Light Communication ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Excess Noise ◽  
Avalanche Breakdown ◽  
Cmos Process ◽  
Noise Characteristics

A new avalanche photodiode device applied to a visible light communication (VLC) system is designed using a standard 0.18 [Formula: see text]m complementary metal oxide semiconductor process. Compared to regular CMOS APD devices, the proposed device adds a [Formula: see text]-well layer above the deep [Formula: see text]-well/[Formula: see text]-substrate structure, and an [Formula: see text]/[Formula: see text] layer is deposited upon it. The [Formula: see text]/[Formula: see text] layer acts as an avalanche breakdown layer of the device, and an STI structure is used to prevent the edge break prematurely. The simulation results shows that the avalanche breakdown voltage is as low as 9.9 V, dark current is below [Formula: see text] A under −9.5 V bias voltage, and the 3 dB bandwidth is of 5.9 GHz. It is due to the use of the 0.18 [Formula: see text]m CMOS process-specific STI protection ring and short-circuits the connection of the deep [Formula: see text]-well/[Formula: see text]-substrate, and the dark current is reduced to be lower than two orders of magnitude compared to regular CMOS APD. Gain and noise characteristics are accurately calculated from Hayat dead-space model applied to this CMOS APD. So, this device’s gain and excess noise factor are 20 and 2.5, respectively.

scholarly journals A 5-nV/√Hz Chopper Negative-R Stabilization Preamplifier for Audio Applications

Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 478
Author(s):  
Jamel Nebhen ◽  
Khaled Alnowaiser ◽  
Stephane Meillere
Keyword(s):  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Chopper Stabilization ◽  
Main Amplifier ◽  
Measurement Results ◽  
Low Noise Preamplifier

This paper presents a low-noise and low-power audio preamplifier. The proposed low-noise preamplifier employs a delay-time chopper stabilization (CHS) technique and a negative-R circuit, both in the auxiliary amplifier to cancel the non-idealities of the main amplifier. The proposed technique makes it possible to mitigate the preamplifier 1/f noise and thermal noise and improve its linearity. The low-noise preamplifier is implemented in 65 nm complementary metal-oxide semiconductor (CMOS) technology. The supply voltage is 1.2 V, while the power consumption is 159 µW, and the core area is 192 µm2. The proposed circuit of the preamplifier was fabricated and measured. From the measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 80 dB, an equivalent-input referred noise of 5 nV/√Hz and a noise efficiency factor (NEF) of 1.9 within the frequency range from 1 Hz to 20 kHz.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

scholarly journals An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1686
Author(s):  
Jian Chen ◽  
Wei Zhang ◽  
Qingqing Sun ◽  
Lizheng Liu
Keyword(s):  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Serial Link ◽  
Ldo Regulator ◽  
28 Nm

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

scholarly journals A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

2017 ◽  
Vol 27 (03) ◽  
pp. 1850047
Author(s):  
Xin Zhang ◽  
Chunhua Wang ◽  
Yichuang Sun ◽  
Haijun Peng
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Low Noise ◽  
Ultra Wideband ◽  
Oxide Semiconductor ◽  
High Linearity ◽  
Low Supply Voltage

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

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