scholarly journals Switched-Biasing Techniques for CMOS Voltage-Controlled Oscillator

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 316
Author(s):  
Cheol-Woo Kang ◽  
Hyunwon Moon ◽  
Jong-Ryul Yang
Keyword(s):  
Phase Noise ◽  
High Speed ◽  
Frequency Conversion ◽  
Flicker Noise ◽  
Current Source ◽  
Corner Frequency ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Advantages And Disadvantages ◽  
Application Systems

A voltage-controlled oscillator (VCO) is a key component to generate high-speed clock of mixed-mode circuits and local oscillation signals of the frequency conversion in wired and wireless application systems. In particular, the recent evolution of new high-speed wireless systems in the millimeter-wave frequency band calls for the implementation of the VCO with high oscillation frequency and low close-in phase noise. The effect of the flicker noise on the phase noise of the VCO should be minimized because the flicker noise dramatically increases as the deep-submicron complementary metal-oxide-semiconductor (CMOS) process is scaled down, and the flicker corner frequency also increases, up to several MHz, in the up-to-date CMOS process. The flicker noise induced by the current source is a major factor affecting the phase noise of the VCO. Switched-biasing techniques have been proposed to minimize the effect of the flicker noise at the output of the VCO with biasing AC-coupled signals at the current source of the VCO. Reviewing the advantages and disadvantages reported in the previous studies, it is analyzed which topology to implement the switched-biasing technique is advantageous for improving the performance of the CMOS VCOs.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

A Scalable Millimetre-Wave Differential CMOS Cross-Coupled VCO for Automotive Radar Application

2018 ◽  
Vol 27 (10) ◽  
pp. 1850158 ◽  
Author(s):  
Rekha Yadav ◽  
Pawan Kumar Dahiya ◽  
Rajesh Mishra
Keyword(s):  
Phase Noise ◽  
Oxide Semiconductor ◽  
Control Voltage ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
Millimetre Wave ◽  
The Impact ◽  
Lc Vco

In this paper, a novel method to realize LC Voltage-Controlled-Oscillator (LC-VCO) operating at 76.2–76.7[Formula: see text]GHz frequency band for microwave RFIC component is presented. The model of cross-coupled differential LC-VCO is designed in 45[Formula: see text]nm technology using Complementary Metal Oxide Semiconductor (CMOS) process for Frequency Modulated Carrier Wave (FMCW) automotive radar sensors and RF transceivers application. The impact of VDD, control voltage and temperature variation on frequency shift, phase noise, and output power has been analyzed to optimize the trade-off between frequency, phase noise, and power requirement. The results depict that LC-VCO dissipates 10.45[Formula: see text]mW power at an operating voltage of 1.5[Formula: see text]V. The phase noise has been observed to be [Formula: see text]90[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset at 76[Formula: see text]GHz carrier frequency. The estimated layout area of IC is [Formula: see text]m2. The result shows the edge of the design over existing techniques.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

scholarly journals A Very Low-phase-noise CMOS Ring VCO Intended for Sensor Interfaces

2021 ◽  
Author(s):  
Mahin Esmaeilzadeh ◽  
Yves Audet ◽  
Mohamed Ali ◽  
Mohamad Sawan
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Silicon Area ◽  
Wide Range ◽  
Extended Frequency ◽  
Sensor Interfaces ◽  
Low Phase Noise ◽  
Analytical Expressions

<p>We describe in the paper a ring voltage-controlled oscillator (VCO) indicating an improved phase noise over a wide range of frequency offsets and an extended frequency/voltage tuning range. The phase noise is improved by leveraging a better linearity approach, while reducing the VCO gain and maintaining wide tuning range. The proposed VCO is a block of a time-domain comparator embedded in a monitoring and readout circuit of an industrial sensor interface. An analytical model is extracted resulting in closed-form expressions for both input-referred noise and phase noise of the VCO. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The prototype of the proposed VCO was implemented and fabricated in a 0.35 µm CMOS process. The integrated VCO consumes 0.903 mW from a 3.3 V supply, when running at its maximum frequency of 9.37 MHz. The measured phase noise of the proposed VCO is -147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the occupied silicon area of circuit is 0.005 mm<sup>2</sup>.</p>

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

scholarly journals Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 529 ◽  
Author(s):  
Abbas Nasri ◽  
Siroos Toofan ◽  
Motahhareh Estebsari ◽  
Abouzar Estebsari
Keyword(s):  
Power Systems ◽  
Phase Noise ◽  
Communication Systems ◽  
Power Grids ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Class Ab ◽  
Triple Frequency ◽  
Measurement Units ◽  
Almost All

Growing deployment of more efficient communication systems serving electric power grids highlights the importance of designing more advanced intelligent electronic devices and communication-enabled measurement units. In this context, phasor measurement units (PMUs) are being widely deployed in power systems. A common block in almost all PMUs is a phase locked oscillator which uses a voltage controlled oscillator (VCO). In this paper, a triple frequency based voltage controlled oscillator is presented with low phase noise and robust start-up. The VCO consists of a detector, a comparator, and triple frequency. A VCO starts-up in class AB, then steadies oscillation in class C with low current oscillation. The frequency of the VCO, which is from 13.17 GHz to 16.03 GHz, shows that the frequency is tripling to 41.14–48.11 GHz. Therefore, its application is not limited to PMUs. This work has been simulated in a standard 0.18 µm CMOS process. The simulated VCO achieves a phase noise of −99.47 dBc/Hz at 1 MHz offset and −121.8 dBc/Hz at 10 MHz offset from the 48.11 GHz carrier.

scholarly journals A 1.8 V 18.13 MHz Inverter-Based On-Chip RC Oscillator with Flicker Noise Suppression Using Logic Transition Voltage Feedback

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1353
Author(s):  
Junsoo Ko ◽  
Minjae Lee
Keyword(s):  
Phase Noise ◽  
Noise Suppression ◽  
Flicker Noise ◽  
Low Frequency ◽  
Cmos Process ◽  
Delay Compensation ◽  
Circuit Delay ◽  
On Chip ◽  
Voltage Feedback ◽  
Transition Voltage

An inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency offset phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 μ W. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are −60.09 dBc/Hz at 1 kHz with a figure of merit (FOM) of 151.35 dB/Hz, and −106.27 dBc/Hz at 100 KHz with an FOM of 157.53 dBc/Hz. The proposed oscillator occupies 0.056 mm2 in a standard 0.18 μ m CMOS process.

scholarly journals A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 935 ◽  
Author(s):  
Arash Hejazi ◽  
YoungGun Pu ◽  
Kang-Yoon Lee
Keyword(s):  
Phase Noise ◽  
Carrier Frequency ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Controlled Oscillator ◽  
Wide Range ◽  
Layout Area ◽  
Low Phase Noise

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

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