scholarly journals Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

2019 ◽  
Vol 8 (10) ◽  
pp. 393-396 ◽  
Keyword(s):  
Computer Aided Design ◽  
Gate Dielectric ◽  
Dielectric Materials ◽  
Electrical Characteristics ◽  
Back Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Low Power Logic ◽  
Aided Design ◽  
Tcad Simulations

In this paper, DC performance of double gate tunnel field effect transistor with heterojunction has been assessed by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Different hetero high-κ dielectric materials like HfO2 , ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using band to band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, attains maximum value of ION as 1.522 × 10-5 A/µm. The subthreshold swing (ss) has also been recorded best as 23.93 mV/dec in comparison with conventional homo dielectric i.e. SiO2 -SiO2 oxide throughout the 50 nm channel of HTFET as 34.22 mV/dec, can serve as better alternative tunnel FETs in low power logic applications.

scholarly journals Performance Analysis of Double Gate Hetero Junction Tunnel Fet

2019 ◽  
Vol 9 (2S3) ◽  
pp. 232-234 ◽  
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistor ◽  
Double Gate ◽  
Cross Sectional ◽  
Tunnel Fet ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design ◽  
Compound Materials ◽  
Tcad Simulations

In this paper, a novel heterojunction tunnel field-effect transistor (HTFET) using Sentaurus technology computer-aided design (TCAD) simulations has been presented. The InAs/GaSb compound materials are used in both single gate heterojunction TFET (SG-HTFET) and Double gate heterojunction TFET (DG-HTFET) with SiO2 gate oxide layer to increase performance of the device.The implemented SG-HTFET and DG-HTFET device are increase the TFET's cross-sectional tunnel area. This result develops the subthreshold swing (SS) by 2.45 times, drive current (ION) is close to 10-6 A/µm, leakage current (IOFF) is close to 10-17 A/µm and also diminish the ambipolarity of the device compared to the TFET.

scholarly journals F-Shaped Tunnel Field-Effect Transistor (TFET) for the Low-Power Application

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 760 ◽  
Author(s):  
Seunghyun Yun ◽  
Jeongmin Oh ◽  
Seokjung Kang ◽  
Yoon Kim ◽  
Jang Hyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Characteristics ◽  
Turn On ◽  
Crowding Effects ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Power Application ◽  
Aided Design

In this report, a novel tunnel field-effect transistor (TFET) named ‘F-shaped TFET’ has been proposed and its electrical characteristics are analyzed and optimized by using a computer-aided design simulation. It features ultra-thin and a highly doped source surrounded by lightly doped regions. As a result, it is compared to an L-shaped TFET, which is a motivation of this work, the F-shaped TFET can lower turn-on voltage (VON) maintaining high on-state current (ION) and low subthreshold swing (SS) with the help of electric field crowding effects. The optimized F-shaped TFET shows 0.4 V lower VON than the L-shaped TFET with the same design parameter. In addition, it shows 4.8 times higher ION and 7 mV/dec smaller average SS with the same VON as that for L-shaped TFET.

scholarly journals Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET

Micromachines ◽  
2018 ◽  
Vol 9 (12) ◽  
pp. 657 ◽  
Author(s):  
Zhaonian Yang ◽  
Yuan Yang ◽  
Ningmei Yu ◽  
Juin Liou
Keyword(s):  
Silicon Germanium ◽  
Computer Aided Design ◽  
Advanced Technology ◽  
Tunnel Fet ◽  
Esd Protection ◽  
Protection Devices ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design ◽  
Tcad Simulations

Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed.

scholarly journals Effects of Back-Gate Bias on Subthreshold Swing of Tunnel Field-Effect Transistor

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1415 ◽  
Author(s):  
Jaehong Lee ◽  
Garam Kim ◽  
Sangwan Kim
Keyword(s):  
Gate Voltage ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Gate Bias ◽  
Back Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this study, the effects of back-gate bias on the subthreshold swing (S) of a tunnel field-effect transistor (TFET) were discussed. The electrostatic characteristics of the back-gated TFET were obtained using technology computer-aided design (TCAD) simulation and were explained using the concepts of turn-on and inversion voltages. As a result, S decreased, when the back-gate voltage increased; this behavior is attributed to the resultant increase in inversion voltage. In addition, it was found that the on–off current ratio of the TFET increased with a decrease in S due to the back-gate voltage.

scholarly journals Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 749 ◽  
Author(s):  
Jang ◽  
Yoon ◽  
Cho ◽  
Jung ◽  
Lee ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Design Parameters ◽  
Channel Height ◽  
Logic Device ◽  
Metal Core ◽  
Design And Optimization ◽  
Channel Thickness ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core–shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 μA/μm, off-state current (Ioff) of 1.09 × 10−12 A/μm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

scholarly journals Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs

Eng ◽  
2021 ◽  
Vol 2 (4) ◽  
pp. 620-631
Author(s):  
Peng Lu ◽  
Can Yang ◽  
Yifei Li ◽  
Bo Li ◽  
Zhengsheng Han
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Gate Dielectric ◽  
Capture Rate ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Threshold Voltage Shift ◽  
Space Applications ◽  
Effect Transistor ◽  
Aided Design

The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

I-Shaped SiGe Fin Tunnel Field-Effect Transistor with High ION/IOFF Ratio

2020 ◽  
Vol 20 (7) ◽  
pp. 4298-4302
Author(s):  
Ryoongbin Lee ◽  
Junil Lee ◽  
Kitae Lee ◽  
Soyoun Kim ◽  
Sihyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Channel Width ◽  
Condensation Process ◽  
Performance Improvements ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design ◽  
Effective Channel

In this paper, we propose an I-shaped SiGe fin tunnel field-effect transistor (TFET) and use technology computer aided design (TCAD) simulations to verify the validity. Compared to conventional Fin TFET on the same footprint, a 27% increase in the effective channel width can be obtained with the proposed TFET. The proposed Fin TFET was confirmed to have 300% boosted on-current (I on), 25% reduced subthreshold swing (SS), and 52% lower off-current (I off) than conventional Fin TFET through TCAD simulation results. These performance improvements are attributed to increased effective channel width and enhanced gate controllability of the I-shaped fin structure. Furthermore, the fabrication process of forming an I-shaped SiGe fin is also presented using the SiGe wet etch. By optimizing the Ge condensation process, an I-shaped SiGe fin with a Ge ratio greater than 50% can be obtained.

scholarly journals Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

Crystals ◽  
2021 ◽  
Vol 11 (2) ◽  
pp. 128
Author(s):  
Zhihua Zhu ◽  
Zhaonian Yang ◽  
Xiaomei Fan ◽  
Yingtao Zhang ◽  
Juin Jei Liou ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Source Region ◽  
Potential Candidate ◽  
Protection Scheme ◽  
Esd Protection ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

scholarly journals Analysis of Current Variation with Work Function Variation in L-Shaped Tunnel-Field Effect Transistor

Micromachines ◽  
2020 ◽  
Vol 11 (8) ◽  
pp. 780
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Young Suh Song ◽  
Sangwan Kim ◽  
Garam Kim
Keyword(s):  
Work Function ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Tunnel Barrier ◽  
Entire Area ◽  
Current Variation ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this paper, an investigation is performed to analyze the L-shaped tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV) with help of technology computer-aided design (TCAD) simulation. Depending on the gate voltage, the three variations occur in transfer curves. The first one is the on-state current (ION) variation, the second one is the hump current (IHUMP) variation, and the last one is ambipolar current (IAMB) variation. According to the simulation results, the ION variation is sensitive depending on the size of the tunneling region and could be reduced by increasing the tunneling region. However, the IHUMP and IAMB variations are relatively irrelevant to the size of the tunneling region. In order to analyze the cause of this difference, we investigated the band-to-band tunneling (BTBT) rate according to WFV cases. The results show that when ION is formed in L-shaped TFET, the BTBT rate relies on the WFV in the whole region of the gate because the tunnel barrier is formed in the entire area where the source and the gate meet. On the other hand, when the IHUMP and IAMB are formed in L-shaped TFET, the BTBT rate relies on the WFV in the edge of the gate.

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