A Preamplifier-Latch Comparator with Reduced Delay Time for High Accuracy Switched-Capacitor Pipelined ADC

2013 ◽  
Vol 303-306 ◽  
pp. 1842-1848 ◽  
Author(s):  
Jin Rong Wu ◽  
Ying Ju ◽  
Zhi Lun Lin ◽  
Chu Lian Lin ◽  
Xiao Chao Li
Keyword(s):  
Delay Time ◽  
High Accuracy ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Transfer Delay ◽  
Offset Voltage ◽  
Process Simulations ◽  
Neutralization Techniques ◽  
Simulation Results ◽  
Peak Value

This paper presents a modified preamplifier-latch comparator for minimum latch delay and minimum input referred noise. The ratio of PMOS/NMOS in cross-coupled inverter is verified theoretically and optimized for minimum comparator delay. The cross-coupled load, the cascaded structure and the capacitor neutralization techniques are adopted to reduce the kickback noise and the input referred offset voltage. The comparator circuit is designed in a TSMC 0.35 um/3.3 V 2P4M CMOS process. Simulations show that the delay time of latch is declined by 18 percent after optimization and the maximum transfer delay time is only 384.5 ps. The peak to peak value of kickback noise is only 0.831uV in case of Vin,max=1.25 V, and the Monte Carlo simulation results show that equivalent input referred offset voltage is 4.56mV.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

Time Delay Model for SRAM Compiler

2013 ◽  
Vol 373-375 ◽  
pp. 1561-1566
Author(s):  
Qiang Song ◽  
Chun Yu Peng ◽  
Hong Gang Zhou ◽  
Shou Biao Tan
Keyword(s):  
Time Delay ◽  
Delay Time ◽  
High Accuracy ◽  
Cmos Process ◽  
Delay Model ◽  
Effective Time

In this paper, we introduced an effective time delay model for SRAM compiler, which represents an important performance of SRAM. Our method divide the delay time into several periods, including decoder delay, word line delay, bit line delay and SA delay. The theory is useful in predicting the delay time when the SRAM size is changed. Simulations by Hsim in 65nm CMOS process proves a high accuracy.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

Model Building and Simulation of the Suspension System for a Robotic Asparagus Harvester

2018 ◽  
Vol 884 ◽  
pp. 69-76
Author(s):  
Ming Bin Min ◽  
Matthew Peebles ◽  
Shen Hin Lim ◽  
Mike Duke ◽  
Chi Kit Au
Keyword(s):  
Model Building ◽  
High Accuracy ◽  
Suspension System ◽  
Acceptable Level ◽  
Mobile Manipulators ◽  
Proposed Model ◽  
The Future ◽  
Simulation Results ◽  
Peak Value

The demand for high accuracy on automated harvesters is getting higher. While system accuracy is lowered by vibration resulted when a robot with sensors and arms is running on the field. Applying suspension system onto these automated harvesters is a solution to reduce the vibration effects and assure required accuracy. This paper presents a model of the suspension system for a robotic asparagus harvester. The simulation results showed that the peak value of vibration was reduced to an acceptable level. Most importantly, the peak deflection of a vibrated platform was decreased to a required range as well. At the end of this paper, a conclusion is drawn. A suspension system is suggested to reduce vibration effects and improve the accuracy of both sensors and picking arms for mobile manipulators. In the future, this suspension system will be fabricated and installed onto a robotic asparagus harvester to validate this proposed model.

Design of the High-Speed High-Resolution Latched Comparator

2013 ◽  
Vol 748 ◽  
pp. 853-858
Author(s):  
Ye Wang ◽  
Yong Sheng Yin ◽  
Lang Wang ◽  
Hong Hui Deng
Keyword(s):  
High Resolution ◽  
High Speed ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Comparison Theory ◽  
Regeneration Time ◽  
Offset Voltage ◽  
Latched Comparator ◽  
Simulation Results ◽  
Offset Error

Based on the latch and comparison theory, a high-speed high-resolution latched comparator is designed in this paper by using a standard 0.18μm/1.8V CMOS process. With the sampling frequency of 400MHz, the Cadence Spectre simulation results show that the regeneration time is around 230ps and only 11.83mV offset voltage, power consumption is 2.12mW, the minimum voltage resolution is 0.2mV without any input offset error. The circuit is applicable for the design of a high-speed high-resolution A/D converter.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

Modeling and Design of Permanent Magnet Vibration-to-Electrical Power Generator’s Induction Coil

2012 ◽  
Vol 588-589 ◽  
pp. 614-617
Author(s):  
Zhi Hua Wang ◽  
Mei Ling Li ◽  
Jian Zhang ◽  
Li Wang ◽  
Yong Xu
Keyword(s):  
Permanent Magnet ◽  
Electrical Power ◽  
Induction Coil ◽  
Test Results ◽  
Coil Design ◽  
Sinusoidal Vibration ◽  
Electrical Generator ◽  
Simulation Results ◽  
Peak Value

The Equivalent Turn Number of Coil (ETNC) is proposed for induction coil design. Simulation results show that the vibrationonthe induction coil’s structure. The optimized coil is composed by two symmetry parts on the condition of sinusoidal vibration. The effective value of output EMF of optimized coil increases 51.39% than uniform coil’s. In the experiment, the optimized and uniform coils are fabricated with 600 turns and comparatively studied in the same vibration-to-electrical generator. The test results show that the peak-to-peak value and effective value of output EMF of the optimized coil can increase up to 52.59% and 48.76%, respectively, compared with the uniform coil.

scholarly journals A Novel Ultrasonic TOF Ranging System Using AlN Based PMUTs

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 284
Author(s):  
Yihsiang Chiu ◽  
Chen Wang ◽  
Dan Gong ◽  
Nan Li ◽  
Shenglin Ma ◽  
...  
Keyword(s):  
Clock Cycle ◽  
High Accuracy ◽  
Ultrasonic Waves ◽  
Oxide Semiconductor ◽  
Average Error ◽  
Cmos Process ◽  
Clock Frequency ◽  
Time Frequency ◽  
Range Finding ◽  
Wide Range

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS

2010 ◽  
Vol 19 (03) ◽  
pp. 519-528 ◽  
Author(s):  
M. PRAMOD ◽  
T. LAXMINIDHI
Keyword(s):  
Continuous Time ◽  
Input Impedance ◽  
Cmos Process ◽  
High Input ◽  
High Input Impedance ◽  
Common Mode ◽  
Standby Power ◽  
Low Distortion ◽  
Simulation Results ◽  
Feedback Circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

Design and Implementation of a 12-Bit 100MS/s ADC

2012 ◽  
Vol 229-231 ◽  
pp. 1507-1510
Author(s):  
Xiang Ning Fan ◽  
Hao Zheng ◽  
Yu Tao Sun ◽  
Xiang Yan
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Stage Structure ◽  
Digital Calibration ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Design And Implementation ◽  
Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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