Potential of 4H-SiC CMOS for High Temperature Applications Using Advanced Lateral p-MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 821-824 ◽  
Author(s):  
Matthaeus Albrecht ◽  
Tobias Erlbacher ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Drain Current ◽  
Transfer Characteristic ◽  
Propagation Delay ◽  
Channel Mobility ◽  
Propagation Delay Time ◽  
Respective Field ◽  
Channel Lengths ◽  
The Impact

In this work, the impact of the n-well doping concentration on the channel mobility and threshold voltage of p-MOSFETs and their applications in CMOS-devices is evaluated. For this purpose lateral p-channel MOSFETs with different channel lengths (L = 800 μm, 10 μm, 5 μm, and 3 μm) and doping concentrations (ND = 1015 cm-3 and 8·1015 cm-3) were fabricated and the respective field-effect mobility was extracted from the transfer-characteristics. Comparable to n-MOSFETs the mobility of p-MOSFETs was found to be the highest for the lowest doping concentration in the channel and the absolute value of the threshold voltage increases with increasing doping concentration [4]. To investigate its suitability for CMOS applications, inverters with different doping concentrations for n-MOSFET (NA = 1015 cm-3 and 1017 cm-3) und p-MOSFET (ND = 1015 cm-3 and 8·1015 cm-3) were built. For logic levels of 0 V and 10 V, the voltage transfer characteristic with the highest input ranges was obtained for a low p-MOSFET and a high n-MOSFET doping concentration. The lowest propagation delay time could be achieved with a low p-MOSFET and a low n-MOSFET doping concentration. At room temperature as well as at high temperatures T = 573 K the drain current of p-MOSFETs with channel lengths below 3 μm is hampered by the series resistance of the source and drain region which limits the performance of CMOS devices.

Improving 5V Digital 4H-SiC CMOS ICs for Operating at 400°C Using PMOS Channel Implantation

2019 ◽  
Vol 963 ◽  
pp. 827-831 ◽  
Author(s):  
Matthaeus Albrecht ◽  
Tobias Erlbacher ◽  
Anton Bauer ◽  
Lothar Frey
Keyword(s):  
Power Supply ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Implantation Dose ◽  
Channel Mobility ◽  
Propagation Delay Time ◽  
The Impact ◽  
Channel Properties ◽  
Input Level ◽  
Effective Channel

In this work, the impact of a shallow aluminum channel implantation on the channel properties of SiC p-MOSFETs and digital SiC CMOS devices is investigated. For this purpose, p-MOSFETs, CMOS inverters and ring oscillators with different channel implantation doses were fabricated and electrically characterized. The threshold voltage of the resulting p-MOSFETs was shifted from-5 V to-3.6 V whereas the effective channel mobility was slightly decreased from 11.8 cm2/Vs to 10.2 cm2/Vs for a p-MOSFET channel implantation dose of 2∙1013 cm-2 compared to the non-implanted channel. The resulting p-MOSFETs enable SiC CMOS logic circuits to operate with a 5 V power supply and to satisfy 5 V TTL input level specification over the whole temperature range of 25°C to 400°C. Furthermore the propagation delay time of inverters was reduced by 80% at 25°C and 40% at 400°C compared to inverters without p-MOSFET channel implantation.

Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

2021 ◽  
Author(s):  
Rishu Chaujar ◽  
Mekonnen Getnet Yirak
Keyword(s):  
Threshold Voltage ◽  
Positive Impact ◽  
Drain Current ◽  
Interface Trap ◽  
Metal Gate ◽  
High K ◽  
Current Threshold ◽  
Subthreshold Voltage ◽  
Output Characteristics ◽  
The Impact

Abstract In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.

scholarly journals Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

Crystals ◽  
2021 ◽  
Vol 11 (9) ◽  
pp. 1150
Author(s):  
Yoanlys Hernandez ◽  
Bernhard Stampfer ◽  
Tibor Grasser ◽  
Michael Waltl
Keyword(s):  
Delay Time ◽  
Propagation Delay ◽  
Operating Conditions ◽  
Physical Models ◽  
Stable Operation ◽  
Reliability Models ◽  
Bias Temperature Instability ◽  
Propagation Delay Time ◽  
Aging Mechanisms ◽  
The Impact

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

scholarly journals Performance analysis of ultrathin junctionless double gate vertical MOSFETs

2019 ◽  
Vol 8 (4) ◽  
Author(s):  
K. E. Kaharudin ◽  
Z. A. F. M. Napiah ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
Ameer F. Roslan
Keyword(s):  
Performance Analysis ◽  
Process Simulation ◽  
Doping Concentration ◽  
Drain Current ◽  
Double Gate ◽  
Subthreshold Slope ◽  
Main Challenge ◽  
Channel Engineering ◽  
The Impact ◽  
Vertical Mosfets

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

scholarly journals Prediction Model for Random Variation in FinFET Induced by Line-Edge-Roughness (LER)

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 455
Author(s):  
Jinwoong Lee ◽  
Taeeon Park ◽  
Hongjoon Ahn ◽  
Jihwan Kwak ◽  
Taesup Moon ◽  
...  
Keyword(s):  
Prediction Model ◽  
Threshold Voltage ◽  
Drain Current ◽  
Ann Model ◽  
Line Edge Roughness ◽  
Threshold Voltages ◽  
Edge Roughness ◽  
Artificial Neural Network Ann ◽  
The Impact ◽  
Random Variation

As the physical size of MOSFET has been aggressively scaled-down, the impact of process-induced random variation (RV) should be considered as one of the device design considerations of MOSFET. In this work, an artificial neural network (ANN) model is developed to investigate the effect of line-edge roughness (LER)-induced random variation on the input/output transfer characteristics (e.g., off-state leakage current (Ioff), subthreshold slope (SS), saturation drain current (Id,sat), linear drain current (Id,lin), saturation threshold voltage (Vth,sat), and linear threshold voltage (Vth,lin)) of 5 nm FinFET. Hence, the prediction model was divided into two phases, i.e., “Predict Vth” and “Model Vth”. In the former, LER profiles were only used as training input features, and two threshold voltages (i.e., Vth,sat and Vth,lin) were target variables. In the latter, however, LER profiles and the two threshold voltages were used as training input features. The final prediction was then made by feeding the output of the first model to the input of the second model. The developed models were quantitatively evaluated by the Earth Mover Distance (EMD) between the target variables from the TCAD simulation tool and the predicted variables of the ANN model, and we confirm both the prediction accuracy and time-efficiency of our model.

Design of JL-CFET(junctionless complementary field effect transistor)-based inverter for low power applications

2021 ◽  
Author(s):  
Sumi Lee ◽  
Yejoo Choi ◽  
Sang Min Won ◽  
Donghee Son ◽  
Hyoung Won Baac ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Performance Metrics ◽  
Drain Current ◽  
Propagation Delay ◽  
Propagation Delay Time ◽  
Capacitance Effect ◽  
Effect Transistor ◽  
Layout Area

Abstract Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (1) a high work function of metal gate and (2) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

The Impact of Fermi Pinning on Thermal Properties of the Instabilities in ZnO TFTs

2006 ◽  
Vol 957 ◽  
Author(s):  
R.B.M. Cross ◽  
M. M. De Souza
Keyword(s):  
Charge Trapping ◽  
Drain Current ◽  
Conduction Band Edge ◽  
Interfacial Region ◽  
Gate Bias ◽  
Trap States ◽  
High Concentration ◽  
Channel Mobility ◽  
High Level ◽  
The Impact

ABSTRACTIn this paper we describe gate bias and temperature induced device instabilities of inverted-staggered ZnO-TFTs. It is shown that low positive and negative gate bias results in the transfer characteristics shifting in a positive and negative direction respectively. It is suggested that this is a consequence of temporary charge trapping at or close to the channel/insulator interface. The degradation of device parameters such as the threshold voltage, subthreshold slope and effective channel mobility is demonstrated at elevated measurement temperatures, suggesting the generation of defects and/or trap states in the interfacial region. In addition, it is postulated from the extracted activation energy of the drain current that the Fermi-level is pinned during the operation of the devices due to the high level of states close to the conduction band edge. These results highlight the relatively ease with which defects could be created at the interface, indicating a high concentration of weak or strained bonds. Both charge trapping and defect creation-induced instabilities appear to be reversible, as all devices regain their original characteristics after a period of relaxation at room temperature.

scholarly journals Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs

2016 ◽  
Vol 11 (1) ◽  
pp. 7-12
Author(s):  
Alberto V. Oliveira ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Operation Mode ◽  
Drain Current ◽  
State Density ◽  
Dynamic Threshold ◽  
Oxide Interface ◽  
Gate Stack ◽  
Al2o3 Layer ◽  
The Impact ◽  
Analog Parameters

One of the main challenging issues for germanium (Ge) devices is the gate stack engineering which determines the interface state density (NIT) and the associated channel/oxide interface quality. This paper shows how this issue can play a role in p-channel Ge MOSFETs considering both the operation mode, i.e., comparing conventional, dynamic threshold voltage (DT, where VBS = VGS) and enhanced dynamic threshold voltage (eDT, where VBS=k*VGS) modes, and the main analog parameters like the Early voltage (VEA) and intrinsic voltage gain (AV). Moreover, the impact of different HfO2/Al2O3 gate stack thicknesses is under evaluation. Although the thinnest Al2O3 layer degrades all evaluated parameters, specifically: lower VEA and AV, higher drain current hysteresis and subthreshold swing (SS) due to the higher NIT, the dynamic threshold voltage showed to be an effective mode to strongly minimize the hysteresis effects and improves up to 60% in eDT (k = 2) mode compared to the conventional mode (k = 0), thanks to the dynamic threshold voltage reduction.

Impact of Al Doping Concentration at Channel Region on Mobility and Threshold Voltage Instability in 4H-SiC Trench N-MOSFETs

2016 ◽  
Vol 858 ◽  
pp. 607-610 ◽  
Author(s):  
Katsuhiro Kutsuki ◽  
Sachiko Kawaji ◽  
Yukihiko Watanabe ◽  
Masatoshi Tsujimura ◽  
Toru Onishi ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
The Other ◽  
Positive Bias ◽  
Al Doping ◽  
Channel Mobility ◽  
Voltage Instability ◽  
Bias Temperature Stress ◽  
Channel Region ◽  
Effective Channel

The effect of Al doping concentration (NA) at channel regions ranging from 1.0×1017 to 4.0×1017 cm-3 on the effective channel mobility of electron (μeff) and the threshold voltage (Vth) instability under the positive bias-temperature-stress conditions has been investigated througu the use of trench-gate 4H-SiC MOSFETs with m-face (1-100) channel regions. It was found that μeff degraded with an increase in NA. On the other hand, the increase of NA enlarged the Vth instability. These results indicate that NA has a large impact not only on the Vth value but also on the channel resistance and reliability in 4H-SiC trench MOSFETs.

High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

2021 ◽  
Vol 14 (1) ◽  
pp. 014003
Author(s):  
Shahab Mollah ◽  
Kamal Hussain ◽  
Abdullah Mamun ◽  
Mikhail Gaevski ◽  
Grigory Simin ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
High Current ◽  
Enhancement Mode ◽  
Recessed Gate
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