Process and Evaluation of High Reliability Reworkable Edge Bond Adhesives for Large Area BGA Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 002018-002053
Author(s):  
Swapan Bhattacharya ◽  
Fei Xie ◽  
Daniel F. Baldwin ◽  
Han Wu ◽  
Kelley Hodge ◽  
...  
Keyword(s):  
High Performance ◽  
Printed Circuit Boards ◽  
Process Development ◽  
High Reliability ◽  
Optimum Process ◽  
Process Conditions ◽  
Harsh Environment ◽  
Mechanical Shock ◽  
Large Area ◽  
Reliability Performance

Reworkable underfills and edge bond adhesives are finding increasing utility in high reliability and harsh environment applications. The ASICs and FPGAs often used in these systems typically require designs incorporating large BGAs and ceramic BGAs. For these high reliability and harsh environment applications, these packages typically require underfill or edge bond materials to achieve the needed thermal cycle, mechanical shock and vibration reliability. Moreover, these applications often incorporate high dollar value printed circuit boards (on the order of thousands or tens of thousands of dollars per PCB) hence the need to rework these assemblies and maintain the integrity of the PCB and high dollar value BGAs. This further complicates the underfill requirements with a reworkability component. Reworkable underfills introduce a number of process issues that can result in significant variability in reliability performance. In contrast, edge bond adhesives provide a high reliability solution with substantial benefits over underfills. One interesting question for the large area BGA applications of reworkable underfills and edge bond materials is the comparison of their reliability performance. This paper presents a study of reliability comparison between two robust selected reworkable underfill and edge bond adhesive in a test vehicle including 11mm, 13mm, and 27mm large area BGAs. Process development for those large area BGA applications was also conducted on the underfill process and edge bond process to determine optimum process conditions. For underfill processing, establishing an underfill process that minimizing/eliminates underfill voids is critical. For edge bond processing, establishing an edge bond that maximizes bond area without encapsulating the solder balls is key to achieving high reliability. In addition, this paper also presents a study of new high performance reworkable edge bond materials designed to improve the reliability of large area BGAs and ceramic BGAs assemblies while maintaining good reworkablity. Four edge bond materials (commercially available) were studied and compared for a test vehicles with 12mm BGAs. The reliability testing protocol included board level thermal cycling (−40 to 125°C), mechanical drop testing (2900 G), and random vibration testing (3 G, 10 – 1000 Hz).

High Reliability and Thermal Performance FCBGA Package

2007 ◽  
Author(s):  
Gino Hung ◽  
Ho-Yi Tsai ◽  
Chun An Huang ◽  
Steve Chiu ◽  
C. S. Hsiao
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Dielectric Material ◽  
High Reliability ◽  
Lead Free ◽  
Molding Process ◽  
Molding Compound ◽  
Reliability Performance ◽  
Low K

A high reliability and high thermal performance molding flip chip ball grid arrays structure which was improved from Terminator FCBGA®. (The structure are shown as Fig. 1) It has many advantages, like better coplanarity, high through put (multi pes for each shut of molding process), low stress, and high thermal performance. In conventional flip chip structure, underfill dispenses and cure processes are a bottleneck due to low through put (dispensing unit by unit). For the high performance demand, large package/die size with more integrated functions needs to meet reliability criteria. Low k dielectric material, lead free bump especially and the package coplanarity are also challenges for package development. Besides, thermal performance is also a key concern with high power device. From simulation and reliability data, this new structure can provide strong bump protection and reach high reliability performance and can be applied for low-K chip and all kind of bump composition such as tin-lead, high lead, and lead free. Comparing to original Terminator FCBGA®, this structure has better thermal performance because the thermal adhesive was added between die and heat spreader instead of epoxy molding compound (EMC). The thermal adhesive has much better thermal conductivity than EMC. Furthermore, this paper also describes the process and reliability validation result.

Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications

2010 ◽  
Vol 2010 (1) ◽  
pp. 000007-000014 ◽  
Author(s):  
Erik Vick ◽  
Scott Goodwin ◽  
Dorota Temple
Keyword(s):  
Optimum Process ◽  
Process Conditions ◽  
Front Side ◽  
Wafer Level ◽  
Large Area ◽  
Test Vehicle ◽  
Dual Damascene ◽  
Damascene Process ◽  
Metal Levels ◽  
Metal Layers

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.

Reliability Analysis of Flip Chip on Board Assemblies Using No-Flow Underfill Materials

1999 ◽  
Author(s):  
Ryan Thorpe ◽  
Daniel F. Baldwin
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Large Area ◽  
Development Activity ◽  
Solder Interconnect ◽  
Chip Processing ◽  
Underfill Flow ◽  
Level 3 ◽  
Reliability Performance

Abstract As a concept to achieve high throughput low cost flip chip on board (FCOB) assembly, a process development activity and reliability assessment is underway, implementing next generation flip chip processing based on large area underfill printing/dispensing, integrated chip placement and underfill flow, and simultaneous solder interconnect reflow and underfill cure. Reported in this work is the assembly of a series of test vehicles to evaluate the reliability of no-flow underfill materials. The reliability performance of four underfill materials is evaluated using six test vehicles. Accelerated reliability tests performed on the test vehicles included liquid/liquid and air/air thermal cycling, autoclave, and J-STD-020 Level 3 preconditioning. No-flow underfill materials tested in this work have demonstrated the ability to survive in excess of 1000 cycles of liquid/liquid thermal shock, survive more than 100 hours of autoclave, and pass J-STD-020 Level 3 preconditioning.

scholarly journals Development of Reliable, High Performance WLCSP for BSI CMOS Image Sensor for Automotive Application

Sensors ◽  
2020 ◽  
Vol 20 (15) ◽  
pp. 4077
Author(s):  
Tianshen Zhou ◽  
Shuying Ma ◽  
Daquan Yu ◽  
Ming Li ◽  
Tao Hang
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
High Reliability ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Automotive Application ◽  
Market Demand ◽  
Wafer Level ◽  
Reliability Performance ◽  
Silicon Vias

To meet the urgent market demand for small package size and high reliability performance for automotive CMOS image sensor (CIS) application, wafer level chip scale packaging (WLCSP) technology using through silicon vias (TSV) needs to be developed to replace current chip on board (COB) packages. In this paper, a WLCSP with the size of 5.82 mm × 5.22 mm and thickness of 850 μm was developed for the backside illumination (BSI) CIS chip using a 65 nm node with a size of 5.8 mm × 5.2 mm. The packaged product has 1392 × 976 pixels and a resolution of up to 60 frames per second with more than 120 dB dynamic range. The structure of the 3D package was designed and the key fabrication processes on a 12” inch wafer were investigated. More than 98% yield and excellent optical performance of the CIS package was achieved after process optimization. The final packages were qualified by AEC-Q100 Grade 2.

New Technology and Developments in Compound Semiconductor Vertical RDR-MOCVD Growth Systems

1994 ◽  
Vol 340 ◽  
Author(s):  
M. McKee ◽  
G.S. Tompa ◽  
P.A. Zawadzki ◽  
A. Thompson ◽  
A. Gurary ◽  
...  
Keyword(s):  
New Technology ◽  
Chemical Vapor ◽  
Rotating Disk ◽  
Easy Access ◽  
Organic Chemical ◽  
Optimum Process ◽  
Process Conditions ◽  
Monitoring And Control ◽  
Large Area ◽  
Wide Range

ABSTRACTCompound semiconductors are at the heart of todays advanced digital and optoelectronic devices. As device production levels increase, so too does the need for high throughput deposition systems. The vertical rotating disk reactor (RDR) has been scaled to dimensions allowing metal organic chemical vapor deposition (MOCVD) on multiple substrates located on a 300 mm diameter platter. This symetric large area reactor affords easy access over a wide range of angles for optical monitoring and control of the growth process. The RDR can be numerically modeled in a straightforward manner, and we have derived scaling rules allowing the prediction of optimum process conditions for larger reactor sizes. The material results give excellent agreement with the modeling, demonstrating GaAs/AlAs structures with <±0.9% thickness uniformities on up to 17-50mm or 4-100mm GaAs substrates. Process issues related to reactor scaling are reviewed. With high reactant efficiencies and short cycle times between growths, through the use of a vacuum loadlock, the costs per wafer are found to be dramatically less than in alternative process reactors. The high reactant utilization, in combination with a dedicated and highly efficient exhaust scrubbing system, minimizes the systems environmental impact.

scholarly journals Programmable and scalable transfer printing with high reliability and efficiency for flexible inorganic electronics

2020 ◽  
Vol 6 (25) ◽  
pp. eabb2393 ◽  
Author(s):  
Chengjun Wang ◽  
Changhong Linghu ◽  
Shuang Nie ◽  
Chenglong Li ◽  
Qianjin Lei ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Adhesive Layer ◽  
Cost Effective ◽  
Electronic Systems ◽  
Transfer Printing ◽  
Large Area ◽  
Surface Microstructures ◽  
High Yields ◽  
Thermal Stimuli

Transfer printing that enables heterogeneous integration of materials in desired layouts offers unprecedented opportunities for developing high-performance unconventional electronic systems. However, large-area integration of ultrathin and delicate functional micro-objects with high yields in a programmable fashion still remains as a great challenge. Here, we present a simple, cost-effective, yet robust transfer printing technique via a shape-conformal stamp with actively actuated surface microstructures for programmable and scalable transfer printing with high reliability and efficiency. The shape-conformal stamp features the polymeric backing and commercially available adhesive layer with embedded expandable microspheres. Upon external thermal stimuli, the embedded microspheres expand to form surface microstructures and yield weak adhesion for reliable release. Systematic experimental and computational studies reveal the fundamental aspects of the extraordinary adhesion switchability of stamp. Demonstrations of this protocol in deterministic assemblies of diverse challenging inorganic micro-objects illustrate its extraordinary capabilities in transfer printing for developing high-performance flexible inorganic electronics.

KEMET SMD Film Capacitors for High Temperature Applications

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000013-000024 ◽  
Author(s):  
Luca Caliari ◽  
Paola Bettacchi ◽  
Evangelista Boni ◽  
Davide Montanari ◽  
Arrigo Gamberini ◽  
...  
Keyword(s):  
High Temperature ◽  
High Reliability ◽  
Ac Loss ◽  
Shock Acceleration ◽  
Hole Drilling ◽  
Harsh Environment ◽  
Mechanical Shock ◽  
Component Level ◽  
Film Capacitor ◽  
Low Leakage

Trends of several applications like down-hole drilling, commercial aviation (e.g. jet engines), heavy industrial and automotive are challenging the capabilities of capacitors and other electronic components. The growing harsh-environment conditions for these applications are: high temperature, high voltage and high current. At the capacitor component level, required features are: very high reliability under mechanical shock, rapid changes in temperature, low leakage current (high insulation resistance), small dimensions, good stability with time and humidity, and high peak withstanding voltage. Capacitors for power-conversion circuitry must maintain a low AC loss and DC leakage at high temperatures. KEMET has recently designed film capacitor series using PEN to address the needs of the above mentioned circuits, in particular regarding the working temperature, voltage and current. This paper will cover technological advances in film capacitor technology to address harsh environment conditions needs, providing test results on temperature, voltage and thermal shock acceleration factor.

ADVANCED ORGANIC SUBSTRATE TECHNOLOGIES FOR HIGH PERFORMANCE, HIGH RELIABILITY ELECTRONICS MINIATURIZATION

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000501-000525
Author(s):  
Susan Bagen ◽  
Dave Alcoe ◽  
Kim Blackwell ◽  
Frank Egitto
Keyword(s):  
High Performance ◽  
Printed Circuit Boards ◽  
High Reliability ◽  
Form Factors ◽  
Dielectric Materials ◽  
Industrial Applications ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Organic Substrates

High reliability applications for high performance computing, military, medical and industrial applications are driving electronics packaging advancements toward increased functionality with decreasing degrees of size, weight and power (SWaP) The substrate technology selected for the electronics package is a key enabling technology towards achieving SWaP. Standard printed circuit boards (PWBs) utilize dielectric materials containing glass cloth, which can limit circuit density and performance, as well as inhibit the ability to achieve reliable assemblies with bare semiconductor die components. Ceramic substrates often used in lieu of PWBs for chip packaging have disadvantages of weight, marginal electrical performance and reliability as compared to organic technologies. Alternative materials including thin, particle-containing organic substrates, liquid crystal polymer (LCP) and microflex enable SWaP, while overcoming the limitations of PWBs and ceramic. This paper will discuss the use of these alternative organic substrate materials to achieve extreme electronics miniaturization with outstanding electrical performance and high reliability. The effect of substrate type on chip-package interaction and resulting reliability will be discussed in detail, and compared to standard PWB and ceramic. Microflex assemblies to achieve extreme miniaturization and atypical form factors driven by implantable and in vivo medical applications are also shown.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

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