Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications

2010 ◽  
Vol 2010 (1) ◽  
pp. 000007-000014 ◽  
Author(s):  
Erik Vick ◽  
Scott Goodwin ◽  
Dorota Temple
Keyword(s):  
Optimum Process ◽  
Process Conditions ◽  
Front Side ◽  
Wafer Level ◽  
Large Area ◽  
Test Vehicle ◽  
Dual Damascene ◽  
Damascene Process ◽  
Metal Levels ◽  
Metal Layers

A TSV test vehicle lot and 3D interposer demonstration lot were successfully fabricated and tested. Fabrication of the TSV test vehicle was accomplished using three process (mask) levels – front-side metal, backside TSV, and backside metal. The TSVs were formed using a vias-last approach with a nominal TSV size of 100μm, and an aspect ratio of 6:1. DRIE bottom clear process conditions were tested which produced 100 % yield on TSV contact chains with up to 540 vias. In addition, optimum process conditions resulted in a TSV resistance of 29 mΩ, and sufficient TSV isolation resistance (> 1MΩ) for the target application. The interposer demonstration lot incorporated five front-side metal levels, one TSV level, and two backside metal levels. The first four metal layers (M1-M4), utilized 2μm Cu and 2μm oxide layers. Metal layers M2-M4 were fabricated using a self-aligned dual damascene process. Each wafer in the demonstration lot had 4 MLM contact chain test structures, with 26400 vias per structure. On two wafers, 100 % yield was achieved on the MLM contact chains. For the dual damascene levels, average contact resistance per via was 4 mΩ. Functional testing was performed on two die from the demonstration lot (die size = 4 cm X 3.7 cm). Over 99 % of the functional nets (circuit paths) passed. Yield on large area test capacitors, tested at wafer level, exceeded 80 %.

Process and Evaluation of High Reliability Reworkable Edge Bond Adhesives for Large Area BGA Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 002018-002053
Author(s):  
Swapan Bhattacharya ◽  
Fei Xie ◽  
Daniel F. Baldwin ◽  
Han Wu ◽  
Kelley Hodge ◽  
...  
Keyword(s):  
High Performance ◽  
Printed Circuit Boards ◽  
Process Development ◽  
High Reliability ◽  
Optimum Process ◽  
Process Conditions ◽  
Harsh Environment ◽  
Mechanical Shock ◽  
Large Area ◽  
Reliability Performance

Reworkable underfills and edge bond adhesives are finding increasing utility in high reliability and harsh environment applications. The ASICs and FPGAs often used in these systems typically require designs incorporating large BGAs and ceramic BGAs. For these high reliability and harsh environment applications, these packages typically require underfill or edge bond materials to achieve the needed thermal cycle, mechanical shock and vibration reliability. Moreover, these applications often incorporate high dollar value printed circuit boards (on the order of thousands or tens of thousands of dollars per PCB) hence the need to rework these assemblies and maintain the integrity of the PCB and high dollar value BGAs. This further complicates the underfill requirements with a reworkability component. Reworkable underfills introduce a number of process issues that can result in significant variability in reliability performance. In contrast, edge bond adhesives provide a high reliability solution with substantial benefits over underfills. One interesting question for the large area BGA applications of reworkable underfills and edge bond materials is the comparison of their reliability performance. This paper presents a study of reliability comparison between two robust selected reworkable underfill and edge bond adhesive in a test vehicle including 11mm, 13mm, and 27mm large area BGAs. Process development for those large area BGA applications was also conducted on the underfill process and edge bond process to determine optimum process conditions. For underfill processing, establishing an underfill process that minimizing/eliminates underfill voids is critical. For edge bond processing, establishing an edge bond that maximizes bond area without encapsulating the solder balls is key to achieving high reliability. In addition, this paper also presents a study of new high performance reworkable edge bond materials designed to improve the reliability of large area BGAs and ceramic BGAs assemblies while maintaining good reworkablity. Four edge bond materials (commercially available) were studied and compared for a test vehicles with 12mm BGAs. The reliability testing protocol included board level thermal cycling (−40 to 125°C), mechanical drop testing (2900 G), and random vibration testing (3 G, 10 – 1000 Hz).

New Technology and Developments in Compound Semiconductor Vertical RDR-MOCVD Growth Systems

1994 ◽  
Vol 340 ◽  
Author(s):  
M. McKee ◽  
G.S. Tompa ◽  
P.A. Zawadzki ◽  
A. Thompson ◽  
A. Gurary ◽  
...  
Keyword(s):  
New Technology ◽  
Chemical Vapor ◽  
Rotating Disk ◽  
Easy Access ◽  
Organic Chemical ◽  
Optimum Process ◽  
Process Conditions ◽  
Monitoring And Control ◽  
Large Area ◽  
Wide Range

ABSTRACTCompound semiconductors are at the heart of todays advanced digital and optoelectronic devices. As device production levels increase, so too does the need for high throughput deposition systems. The vertical rotating disk reactor (RDR) has been scaled to dimensions allowing metal organic chemical vapor deposition (MOCVD) on multiple substrates located on a 300 mm diameter platter. This symetric large area reactor affords easy access over a wide range of angles for optical monitoring and control of the growth process. The RDR can be numerically modeled in a straightforward manner, and we have derived scaling rules allowing the prediction of optimum process conditions for larger reactor sizes. The material results give excellent agreement with the modeling, demonstrating GaAs/AlAs structures with <±0.9% thickness uniformities on up to 17-50mm or 4-100mm GaAs substrates. Process issues related to reactor scaling are reviewed. With high reactant efficiencies and short cycle times between growths, through the use of a vacuum loadlock, the costs per wafer are found to be dramatically less than in alternative process reactors. The high reactant utilization, in combination with a dedicated and highly efficient exhaust scrubbing system, minimizes the systems environmental impact.

Ultra-fine Line Multi-Redistribution Layers with 10 μm Pitch Micro-Vias for Wafer Level and Panel Level Packaging realized by an innovative Excimer Laser Dual Damascene Process

2017 ◽  
Vol 2017 (1) ◽  
pp. 000120-000125 ◽  
Author(s):  
Robert Gernhardt ◽  
Friedrich Müller ◽  
Markus Woehrmann ◽  
Habib Hichri ◽  
Karin Hauck ◽  
...  
Keyword(s):  
Thin Film ◽  
Excimer Laser ◽  
Seed Layer ◽  
New Technologies ◽  
Dielectric Materials ◽  
Wafer Level ◽  
Fine Line ◽  
Dual Damascene ◽  
Damascene Process ◽  
Dry Film

Abstract Multi-chip integrated Fan-Out packages and high I/O CSPs demands for higher routing density on wafer level. Due to that, the classical mask aligner lithography and photosensitive thin-film polymers used for BEOL reach its limits and new technologies and materials are necessary to generate lines and space down to two μm. These multi-metal layers set also higher demands on the mechanical properties of the materials. This paper presents a new excimer laser dual damascene process for ultra-fine routing for BEOL. Various materials like low cure temperature polyimide, BCB and 15-μm thick dry-film ABF material are structured by using an excimer laser stepper with a reticle mask to realize feature size below four μm with a high throughput. Micro-vias with a diameter below five μm are realized with high aspect ratio, which overcome the photolithographic limitations of the common used photosensitive thin-film polymers. The laser structuring allows to use innovative dielectric materials for WLP with optimized mechanical and electrical parameters for example inorganic filled polymers like dry-film ABF materials, which do not have to be photosensitive. The ablations depth per laser pulse and the cross-section of the ablated structures in dependence of the ablation parameters was investigated. The depth of embedded lines was set by number of pulses aside of integrated micro-vias. The lines and micro-vias were metallized with copper by galvanic process and the following CMP step removes the copper outside the ablated structures. The CMP removes only the copper and the metal of the seed-layer, which has the functions of an adhesion and barrier layer, stays intact. The under-etching of the conventional wet etch seed layer removal is a major problem for the fine line structures realized by the Laser Dual Damascene process. Due to that, the removal of the seed layer (usually titan) was investigated and it could be shown, that this layer can be removed by the excimer laser system. The stepper like system allows a sub-micron alignment accuracy with no need of a capture pad of the embedded lines. Test structures have been designed and fabricated with lines and spaces below 10 μm to demonstrate the dense multi-layer routing capability where the excellent reliability can be proven by air to air thermal cycling (from −55°C up to 125°C), current leakage and electro migration test.

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

2000 ◽  
Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Front Side ◽  
Automatic Determination ◽  
Metal Line ◽  
New Approach ◽  
Metal Layers

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

Inorganic Si-O-C Antireflection Coating at 193 nm for Cu Dual Damascene Process

2003 ◽  
Vol 150 (1) ◽  
pp. G58 ◽  
Author(s):  
Sang-Yun Lee ◽  
Yong-Bae Kim ◽  
Jeong Soo Byun
Keyword(s):  
Antireflection Coating ◽  
Dual Damascene ◽  
Damascene Process ◽  
193 Nm

Analyzing the Effect of Fiber, Yarn and Fabric Variables on Bagging Behavior of Single Jersey Weft Knitted Fabrics

2013 ◽  
Vol 8 (3) ◽  
pp. 155892501300800 ◽  
Author(s):  
Mitra Karimian ◽  
Hossein Hasani ◽  
Saeed Ajeli
Keyword(s):  
Optimum Process ◽  
Process Conditions ◽  
Knitted Fabrics ◽  
Yarn Twist ◽  
Fabric Density ◽  
Fabric Structure ◽  
Controllable Factors ◽  
Yarn Count ◽  
The Individual ◽  
Single Jersey

This research investigates the effect of fiber, yarn and fabric variables on the bagging behavior of single jersey weft knitted fabrics interpreted in terms of bagging fatigue percentage. In order to estimate the optimum process conditions and to examine the individual effects of each controllable factor on a particular response, Taguchi's experimental design was used. The controllable factors considered in this research are blending ratio, yarn twist and count, fabric structure and fabric density. The findings show that fabric structure has the largest effect on the fabric bagging. Factor yarn twist is second and is followed by fabric density, blend ratio and yarn count. The optimum conditions to achieve the least bagging fatigue ratio were determined.

Study on the Enzyme Desizing Process for Cotton Fabric Using Ultrasonication

2011 ◽  
Vol 331 ◽  
pp. 261-264 ◽  
Author(s):  
Qi Ming Zhao ◽  
Shan Yan Zhang
Keyword(s):  
Cotton Fabric ◽  
Ph Value ◽  
Orthogonal Experiment ◽  
Research Result ◽  
Strength Loss ◽  
Cotton Fabrics ◽  
Optimum Process ◽  
Process Conditions ◽  
Fabric Strength ◽  
Enzyme Dosage

The auxiliary devices of ultrasonic treatment was designed and manufactured. The cotton fabric was desized using 2000L desizing enzyme with the conventional enzyme desizing process and ultrasonic enzyme desizing process respectively. Through the orthogonal experiment, the optimum process conditions of conventional enzyme desizing process and ultrasonic enzyme desizing process were determined. For the conventional enzyme desizing process, the optimized desizing conditions of cotton fabrics were: desizing enzyme dosage was 1.5g/l, temperature was 80°C, PH value was 6, and time was 60mins. The optimum process conditions of ultrasonic enzyme desizing process were: desizing enzyme dosage was 1.5g/l, temperature was 50°C, PH value was 6 and time was 45minutes. The research result indicates that, under the same desizing condition, ultrasonication can improve the desizing percentage and whiteness of cotton fabric, but the fabric strength loss increases slightly. And for the same required desizing percentage, the ultrasonic enzyme desizing process saved time and reduced the temperature of experiments compared with traditional enzyme desizing process

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