scholarly journals Simple Current-Mode Squaring and Square-Rooting Circuits: Applications of MO-CCCCTA

2021 ◽  
Vol 18 (23) ◽  
pp. 721
Author(s):  
Suvajit Roy ◽  
Tapas Kumar Paul ◽  
Radha Raman Pal
Keyword(s):  
Power Dissipation ◽  
Current Mode ◽  
Transfer Characteristic ◽  
Cmos Process ◽  
Temperature Drift ◽  
Transconductance Amplifier ◽  
Static Power ◽  
Linearity Error ◽  
Design Ideas ◽  
Characteristic Measurement

This work provides new designs of simple current-mode squaring and square-rooting circuits using multiple-output current controlled current conveyor transconductance amplifier (MO-CCCCTA) as an active building block. Since the proposed circuits need no other external components, they are capable of high-frequency operation and well fitted for IC fabrication. Furthermore, they are insensitive to ambient temperature and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA. Additionally, the effects of MO-CCCCTA non-idealities on the designed circuits have also been investigated and discussed. Simulation results generated through PSPICE software using TSMC 0.18 µm CMOS process parameters have been presented to justify the theoretical analysis. The static power consumption, bandwidth, and maximum linearity error in dc transfer characteristic measurement for the square-rooting circuit are found to be 0.17 mW, 445.63 MHz and 1.12 %, while for the squaring circuit they are 0.326 mW, 61.15 MHz and 2.38 %, respectively. The application of the reported circuits as a 2-input vector summation circuit has also been included to strengthen the design ideas. HIGHLIGHTS Simple structures of fully integrable current-mode squarers and square-rooters with low component count and lower power dissipation The circuits are insensitive to temperature drift and their gains can be controlled easily by adjusting the bias currents of MO-CCCCTA Bandwidth, static power dissipation, linearity error of square-rooter are 445.63 MHz, 0.17 mW & ≤ 1.12 %; and for the squarer 61.15 MHz, 0.326 mW & 2.38 %, respectively GRAPHICAL ABSTRACT

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
Vol 1 (2) ◽  
pp. 1-7
Author(s):  
Krishna B.T. ◽  
mohaseena Salma Shaik.
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high-frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

scholarly journals New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources

2015 ◽  
Vol 2015 ◽  
pp. 1-11 ◽  
Author(s):  
Mona Moradi ◽  
Reza Faghih Mirzaee ◽  
Keivan Navi
Keyword(s):  
Integrated Circuit ◽  
Power Dissipation ◽  
Field Effect Transistors ◽  
Current Source ◽  
Integrated Design ◽  
Current Mode ◽  
Constant Current ◽  
Constant Current Source ◽  
Static Power ◽  
Current Flows

Novel designs of current-mode Ternary minimum (AND) and maximum (OR) are proposed in this paper based on Carbon NanoTube Field Effect Transistors (CNTFET). First, these Ternary operators are designed separately. Then, they are combined together in order to generate both outputs concurrently in an integrated design. This integration results in the elimination of common parts when both functions are required at the same time. The third proposed current-mode integrated circuit generates both ternary operators with the usage of only 30 transistors. The new designs are composed of three main parts: (1) the part which converts current to voltage; (2) threshold detectors; and (3) the parallel paths through which the output current flows. Unlike the previously presented structure, there is no need for any constant current source within the new designs. This elimination leads to less static power dissipation. The second proposed current-mode segregated Ternary minimum operates 43% faster and consumes 40% less power in comparison with a previously presented structure.

SYNTHESIS OF CURRENT DIFFERENCING TRANSCONDUCTANCE AMPLIFIER-BASED CURRENT LIMITERS AND ITS APPLICATIONS

2011 ◽  
Vol 20 (02) ◽  
pp. 185-206 ◽  
Author(s):  
WORAPONG TANGSRIRAT ◽  
TATTAYA PUKKALANUN ◽  
WANLOP SURAKAMPONTORN
Keyword(s):  
Piecewise Linear ◽  
Current Mode ◽  
Building Blocks ◽  
Transfer Characteristic ◽  
Piecewise Linear Function ◽  
External Bias ◽  
Full Wave ◽  
Transconductance Amplifier ◽  
Electronically Tunable ◽  
Current Differencing Transconductance Amplifier

A synthesis of analog current limiter (CL) building blocks based on a current differencing transconductance amplifier (CDTA) is proposed. The breakpoint and the slope of the resulting transfer characteristic obtained from the proposed CDTA-based CL are electronically programmable through the external bias currents. To demonstrate versatility of the proposed electronically tunable CLs, some nonlinear applications to programmable current-mode precision full-wave rectifiers and piecewise-linear function approximation generators are also presented. PSPICE simulation and experimental results confirm the effectiveness of the proposed circuits.

scholarly journals A 1-nS 1-V Sub-1-µW Linear CMOS OTA with Rail-to-Rail Input for Hz-Band Sensory Interfaces

Sensors ◽  
2020 ◽  
Vol 20 (11) ◽  
pp. 3303
Author(s):  
Jacek Jakusz ◽  
Waldemar Jendernalik ◽  
Grzegorz Blakiewicz ◽  
Miron Kłosowski ◽  
Stanisław Szczepański
Keyword(s):  
Harmonic Distortion ◽  
Low Frequency ◽  
Cmos Technology ◽  
Channel Length ◽  
Temperature Drift ◽  
Nanometer Cmos ◽  
Rail To Rail ◽  
Transconductance Amplifier ◽  
Current Converter ◽  
Linearity Error

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-Vpp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-Vpp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

HIGH-FREQUENCY LINEAR MULTIPLE-OUTPUT CMOS TRANSCONDUCTANCE AMPLIFIER FOR CURRENT-MODE FILTERS

2006 ◽  
Vol 15 (05) ◽  
pp. 701-717 ◽  
Author(s):  
HSIAO WEI SU ◽  
YICHUANG SUN
Keyword(s):  
High Frequency ◽  
Dynamic Range ◽  
Low Voltage ◽  
Filter Design ◽  
Current Mode ◽  
Cmos Process ◽  
Common Mode ◽  
Differential Input ◽  
Transconductance Amplifier ◽  
Linear Differential

A high-frequency highly linear tunable CMOS multiple-output operational transconductance amplifier (MO-OTA) for fully balanced current-mode OTA and capacitor (OTA-C) filters is presented. The MO-OTA is based on the cross-coupled pairs at the input and provides two pairs of differential outputs. A simple common-mode feedback (CMFB) circuit to stabilize the DC output levels of the MO-OTA is also proposed and two such CMFB circuits are used by the MO-OTA. The proposed MO-OTA is suitable for relatively low voltage (2.5 V) applications as its circuit has only two MOS transistors between the supply and ground rails. Simulated in a TSMC 0.25 μm CMOS process using PSpice, the MO-OTA has at least ± 0.3 V linear differential input signal swing with a single 2.5 V power supply and operates up to 1 GHz frequency. The MO-OTA has a THD less than -46 dB for a differential input voltage of 0.9 Vp-p at 10 MHz, dynamic range (DR) at THD = -46 dB is over 50 dB, and power consumption (with the common-mode feedback circuit) is below 8 mW for the whole tuning range. A fully balanced multiple loop feedback current-mode OTA-C filter example using the proposed MO-OTA is presented. This example also shows that the current-mode follow-the-leader-feedback (FLF) structure can achieve good performances for OTA-C filter design.

scholarly journals Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology

2020 ◽  
Vol 9 (1) ◽  
pp. 19
Author(s):  
Mona Moradi
Keyword(s):  
Power Dissipation ◽  
Digital Signal ◽  
Current Mode ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Digital Signal Processors ◽  
The Arts ◽  
Threshold Voltages ◽  
Static Power ◽  
Signal Processors

Adder core respecting to its various applications in VLSI circuits and<br />systems is considered as the most critical building block in microprocessors,<br />digital signal processors and arithmetic operations. Novel designs of a low<br />power and complexity Current Mode 1-bit Full Adder cell based on<br />CNTFET technology has been presented in this paper. Three major parts<br />construct their structures; 1) the first part that converts current to voltage; 2)<br />threshold detectors (TD); and 3) parallel paths to convey the output currents<br />flow. Adjusting threshold voltages which are significant factor for setting<br />threshold detectors switching point has been achieved by means of CNTFET<br />technology. It would bring significant improvements in adjusting threshold<br />voltages, regarding to its unique characterizations. Simple design, less<br />transistor counts and static power dissipation and better performance<br />comparing previous designs could be considered as some advantages of the<br />novel designs.

scholarly journals Design of Linear Feedback Shift Register for Low Power Applications

2021 ◽  
Vol 9 (VII) ◽  
pp. 3912-3918
Author(s):  
K. Manju Bhargavi
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Current Mode ◽  
Shift Register ◽  
Linear Feedback Shift Register ◽  
Linear Feedback ◽  
Current Mode Logic ◽  
Comparison Results ◽  
Static Power ◽  
Feedback Shift Register

This paper presents the design & implementation of the Linear Feedback Shift Register (LFSR) using the Mentor Graphics tool in 90nm technology. LFSR’s have a wide variety of applications. They are used in pseudo-random variety generation, whitening sequences and pseudo-noise sequences. MOS current-mode logic (MCML) and Dynamic current-mode logic (DYCML) are employed to design an LFSR. MCML is widely used in high-speed applications and these MCML circuits are based on current steering logic. The advantages of the MCML method are that they have high noise immunity due to their differential nature of inputs. The disadvantage of MCML approach is static power dissipation. To overcome these issues of MCML logic, Dynamic CML logic is used. Its advantages include low static power dissipation and high performance. This paper shows the comparison results of CMOS, Dynamic CML and MCML designs in terms of delay, power and transistor count.

scholarly journals Single VDTA Based Dual Mode Single Input Multioutput Biquad Filter

2016 ◽  
Vol 2016 ◽  
pp. 1-10 ◽  
Author(s):  
Rajeshwari Pandey ◽  
Neeta Pandey ◽  
Navin Singhal
Keyword(s):  
Current Mode ◽  
Angular Frequency ◽  
Cmos Process ◽  
Dual Mode ◽  
Biquad Filter ◽  
Transconductance Amplifier ◽  
Low Pass ◽  
Single Input ◽  
Band Pass ◽  
High Pass

This paper presents a dual mode, single input multioutput (SIMO) biquad filter configuration using single voltage differencing transconductance amplifier (VDTA), three capacitors, and a grounded resistor. The proposed topology can be used to synthesize low pass (LP), high pass (HP), and band pass (BP) filter functions. It can be configured as voltage mode (VM) or current mode (CM) structure with appropriate input excitation choice. The angular frequency (ω0) of the proposed structure can be controlled independently of quality factor (Q0). Workability of the proposed biquad configuration is demonstrated through PSPICE simulations using 0.18 μm TSMC CMOS process parameters.

scholarly journals Resistorless Current-Mode First-Order All-Pass Filter with Electronic Tuning Employing Low-Voltage CBTA and Grounded Capacitor

2017 ◽  
Vol 27 (02) ◽  
pp. 1850031 ◽  
Author(s):  
Norbert Herencsar ◽  
Jaroslav Koton ◽  
Abhirup Lahiri ◽  
Umut E. Ayten ◽  
Mehmet Sagbas
Keyword(s):  
Low Voltage ◽  
Current Mode ◽  
Monte Carlo Analysis ◽  
Superior Performance ◽  
Sensitivity Analyses ◽  
Cmos Process ◽  
Pass Filter ◽  
First Order ◽  
Transconductance Amplifier ◽  
Electronic Tuning

In this paper, a new realization of a current-mode first-order all-pass filter (APF) using a single active building block (ABB) and one grounded capacitor is presented. As the ABB, the current backward transconductance amplifier (CBTA) is used, which is one of the most recently reported active elements in the literature. The theoretical results are in detail verified by numerous SPICE simulations using a new low-voltage implementation of CBTA. In the design, the PTM 90[Formula: see text]nm level-7 CMOS process BSIM3v3 parameters with [Formula: see text]0.45[Formula: see text]V supply voltages were used. The proposed resistorless CBTA-C APF provides easy electronic tuning of the pole frequency in the frequency range from 763[Formula: see text]kHz to 17.6[Formula: see text]MHz, which is more than one decade. Maximum power dissipation of the circuit is 828[Formula: see text][Formula: see text]W at bias current 233[Formula: see text][Formula: see text]A. Nonideal, parasitic effects, sensitivity analyses, temperature and noise variation, current swing capability, and Monte Carlo analysis results are also provided. Compared to prior state-of-the-art works, the proposed CBTA-C APF has achieved the highest figure of Merit value, which proves its superior performance.

Sign in / Sign up

Export Citation Format

Share Document