Flexible silicon nanowires sensor for acetone detection on plastic substrates

2021 ◽  
Author(s):  
Kuibo Lan ◽  
Zhi Wang ◽  
Xiaodong Yang ◽  
Junqing Wei ◽  
Yuxiang Qin ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
High Performance ◽  
Underlying Mechanism ◽  
Environmental Safety ◽  
Cmos Process ◽  
Plastic Substrates ◽  
Irregular Shapes ◽  
Good Potential ◽  
Mechanical Bending ◽  
Acetone Detection

Abstract Acetone commonly exists in daily life and is harmful to human health, therefore the convenient and sensitive monitoring of acetone is highly desired. In addition, flexible sensors have the advantages of light-weight, conformal attachable to irregular shapes, etc. In this study, we fabricated high performance flexible silicon nanowires (SiNWs) sensor for acetone detection by transferring the monocrystalline Si film and metal-assisted chemical etching method on polyethylene terephthalate (PET). The SiNWs sensor enabled detection of gaseous acetone with a concentration as low as 0.1 parts per million (ppm) at flat and bending states. The flexible SiNWs sensor was compatible with the CMOS process and exhibited good sensitivity, selectivity and repeatability for acetone detection at room temperature. The flexible sensor showed performance improvement under mechanical bending condition and the underlying mechanism was discussed. The results demonstrated the good potential of the flexible SiNWs sensor for the applications of wearable devices in environmental safety, food quality, and healthcare.

Laser Thermal Processing of Nanowires

2007 ◽  
Author(s):  
Nipun Misra ◽  
Yaoling Pan ◽  
Costas P. Grigoropoulos
Keyword(s):  
Silicon Nanowires ◽  
Flexible Electronics ◽  
Thermal Processing ◽  
High Performance ◽  
Flexible Substrates ◽  
New Paradigm ◽  
Plastic Substrates ◽  
Numerical Predictions ◽  
Nanoscale Electronics ◽  
Laser Thermal Processing

Semiconductor nanowires offer an alternative bottom-up route for nanoscale electronics and photonics application. The possibility of combining nanowires with cheap flexible substrates in the form of nanowire thin-films or composite materials composed of nanowires has opened up a new paradigm for inorganic semiconductor based technologies on flexible substrates. Recently, thin film transistors have been fabricated on plastic substrates based on this technique. This paper discusses laser thermal processing of nanowires as an alternative to conventional thermal processing. Ultra-short pulsed lasers allow for localized energy deposition into nanowires and can therefore enable thermal processing of nanowires on sensitive substrates such as plastics. Laser-based annealing of ion-implanted silicon nanowires is investigated for application in high performance flexible electronics. The efficacy of laser processing is examined through studies of the effect of number of pulses and incident fluence levels on conductance of the nanowires. Finally, numerical predictions of the absorption in the nanowires are presented.

scholarly journals A Novel Fast-Locking ADPLL Based on Bisection Method

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1382
Author(s):  
Xiaoying Deng ◽  
Huazhang Li ◽  
Mingcheng Zhu
Keyword(s):  
High Performance ◽  
Tuning Range ◽  
Frequency Control ◽  
Control Word ◽  
Cmos Process ◽  
Bisection Method ◽  
Reference Frequency ◽  
Wide Tuning Range ◽  
Cascade Structure ◽  
And Control

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY
Keyword(s):  
Low Power ◽  
Electromagnetic Interference ◽  
Continuous Time ◽  
High Speed ◽  
High Performance ◽  
Process Variations ◽  
Cmos Process ◽  
Power Circuit ◽  
Crosstalk Cancellation ◽  
Circuit Components

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

scholarly journals Nanostructure-Enhanced Surface Acoustic Waves Biosensor and Its Computational Modeling

2009 ◽  
Vol 2009 ◽  
pp. 1-11 ◽  
Author(s):  
Guigen Zhang
Keyword(s):  
Acoustic Waves ◽  
High Performance ◽  
Surface Acoustic Waves ◽  
Active Surface ◽  
Underlying Mechanism ◽  
Saw Sensor ◽  
Saw Devices ◽  
Operational Capabilities ◽  
Sensing Platform ◽  
Enhanced Surface

Surface acoustic wave (SAW) devices are considered to be very promising in providing a high-performance sensing platform with wireless and remote operational capabilities. In this review, the basic principles of SAW devices and Love-mode SAW-based biosensors are discussed first to illustrate the need for surface enhancement for the active area of a SAW sensor. Then some of the recent efforts made to incorporate nanostructures into SAW sensors are summarized. After that, a computational approach to elucidate the underlying mechanism for the operations of a Love-mode SAW biosensor with nanostructured active surface is discussed. Finally, a modeling example for a Love-mode SAW sensor with skyscraper nanopillars added to in its active surface along with some selected results is presented.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

scholarly journals Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3370 ◽  
Author(s):  
Saghi Forouhi ◽  
Rasoul Dehghani ◽  
Ebrahim Ghafar-Zadeh
Keyword(s):  
High Performance ◽  
Life Science ◽  
Dynamic Range ◽  
Current Mode ◽  
Capacitive Sensor ◽  
Oxide Semiconductor ◽  
Capacitance Measurement ◽  
Biological Research ◽  
Cmos Process ◽  
Capacitive Sensors

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

47.1: High Performance Plastic Substrates for Active Matrix Flexible FPD

2003 ◽  
Vol 34 (1) ◽  
pp. 1325 ◽  
Author(s):  
Simone Angiolini ◽  
Mauro Avidano ◽  
Roberto Bracco ◽  
Carlo Barlocco ◽  
Nigel D. Young ◽  
...  
Keyword(s):  
High Performance ◽  
Active Matrix ◽  
Plastic Substrates

Selective Use of High Performance Cementitious Composites in Concrete Structures

2008 ◽  
Vol 400-402 ◽  
pp. 27-36
Author(s):  
Christopher K.Y. Leung
Keyword(s):  
High Performance ◽  
Concrete Structures ◽  
Cementitious Composites ◽  
Conventional Concrete ◽  
Practical Applications ◽  
Concrete Members ◽  
High Performance Fiber ◽  
Cast Concrete ◽  
Good Potential ◽  
Concrete Science

Recent advancements in concrete science and technology have made possible the development of high performance fiber reinforced cementitious composites (HPFRCC) with excellent mechanical properties and long-term durability. However, the costs of these materials are many times that of conventional concrete and the construction of complete structures with them is hard to justify. The strategic application of high performance materials, in selected parts of concrete structures, can bring along higher performance/cost and wider acceptance of the material in practice. This paper will investigate several examples of selective HPFRCC application, including the fabrication of permanent formwork for durability enhancement, the replacement of steel reinforcements at the anchorage zone of post-tensioned members to relieve the steel congestion problem as well as the development of simple and narrow joints for pre-cast concrete members. Based on the experimental results obtained so far, the selected use of HPFRCC in concrete structures appears to have good potential for practical applications.

scholarly journals EXPERIENCE OF APPLICATION HIGH PERFORMANCE CEMENT COMPOSITES FOR CREATING DURABLE SCULPTURAL ELEMENTS

2017 ◽  
Vol 3 ◽  
pp. 286
Author(s):  
Genadijs Sahmenko ◽  
Sandis Aispurs ◽  
Aleksandrs Korjakins
Keyword(s):  
Water Absorption ◽  
High Performance ◽  
Cement Composite ◽  
Cement Composites ◽  
Freezing And Thawing ◽  
Initial Water ◽  
Good Potential ◽  
Freezing And Thawing Cycles ◽  
Material Ductility ◽  
And Control

Traditionally, sculptural and decorative elements of building facades are created from mortar mixes based on lime, gypsum or Portland cement. Generally these materials have porous and permeable structure, which determines their accelerated degradation, especially in the aggressive environment of modern cities. High performance cement composites (HPCC) have been considered for production and restoration of sculptural elements in historical buildings. For this purpose, fine-graded, multi-component and highly workable mixes were elaborated. Mix compositions were modified with micro-fillers, plasticizing and stabilizing admixtures, as well as fibers to improve material ductility and control shrinkage cracking. Basic mechanical properties and durability (such as water absorption, frost resistance) were determined and two types of HPCC were compared (>50 MPa: HPCC and >120 MPa: UHPCC). It has been confirmed that cement composite mixes are characterized by self-consolidating effect, high compressive strength, extremely high resistance versus freezing and thawing cycles and low water absorption. Surface quality was evaluated and initial water absorption (tube tests) were performed for laboratory samples and real sculptural elements after 5 years of exploitation. The results confirmed good potential for using HPCC for creating more attractive and durable architectural shapes and façade elements compared to elements made using traditional cement and lime mortar.

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